xref: /linux/Documentation/devicetree/bindings/sound/fsl,sai.yaml (revision 6f7e6393d1ce636bb7ec77a7fe7b77458fddf701) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale Synchronous Audio Interface (SAI).
8
9maintainers:
10  - Shengjiu Wang <shengjiu.wang@nxp.com>
11
12description: |
13  The SAI is based on I2S module that used communicating with audio codecs,
14  which provides a synchronous audio interface that supports fullduplex
15  serial interfaces with frame synchronization such as I2S, AC97, TDM, and
16  codec/DSP interfaces.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - enum:
23              - fsl,imx6ul-sai
24              - fsl,imx7d-sai
25          - const: fsl,imx6sx-sai
26
27      - items:
28          - enum:
29              - fsl,imx8mm-sai
30              - fsl,imx8mn-sai
31              - fsl,imx8mp-sai
32          - const: fsl,imx8mq-sai
33
34      - items:
35          - enum:
36              - fsl,imx6sx-sai
37              - fsl,imx7ulp-sai
38              - fsl,imx8mq-sai
39              - fsl,imx8qm-sai
40              - fsl,imx8ulp-sai
41              - fsl,imx93-sai
42              - fsl,imx95-sai
43              - fsl,vf610-sai
44      - items:
45          - enum:
46              - fsl,imx94-sai
47              - fsl,imx952-sai
48          - const: fsl,imx95-sai
49
50  reg:
51    maxItems: 1
52
53  clocks:
54    items:
55      - description: The ipg clock for register access
56      - description: master clock source 0 (obsoleted)
57      - description: master clock source 1
58      - description: master clock source 2
59      - description: master clock source 3
60      - description: PLL clock source for 8kHz series
61      - description: PLL clock source for 11kHz series
62    minItems: 4
63
64  clock-names:
65    oneOf:
66      - items:
67          - const: bus
68          - const: mclk0
69          - const: mclk1
70          - const: mclk2
71          - const: mclk3
72          - const: pll8k
73          - const: pll11k
74        minItems: 5
75      - items:
76          - const: bus
77          - const: mclk1
78          - const: mclk2
79          - const: mclk3
80          - const: pll8k
81          - const: pll11k
82        minItems: 4
83
84  power-domains:
85    maxItems: 1
86
87  dmas:
88    minItems: 1
89    maxItems: 2
90
91  dma-names:
92    minItems: 1
93    items:
94      - enum: [ rx, tx ]
95      - const: tx
96
97  interrupts:
98    items:
99      - description: receive and transmit interrupt
100
101  ports:
102    $ref: /schemas/graph.yaml#/properties/ports
103    properties:
104      port@0:
105        $ref: audio-graph-port.yaml#
106        unevaluatedProperties: false
107        description: port for TX and RX
108
109      port@1:
110        $ref: audio-graph-port.yaml#
111        unevaluatedProperties: false
112        description: port for TX only
113
114      port@2:
115        $ref: audio-graph-port.yaml#
116        unevaluatedProperties: false
117        description: port for RX only
118
119  big-endian:
120    description: |
121      required if all the SAI registers are big-endian rather than little-endian.
122    type: boolean
123
124  fsl,dataline:
125    $ref: /schemas/types.yaml#/definitions/uint32-matrix
126    description: |
127      Configure the dataline. It has 3 value for each configuration
128    maxItems: 16
129    items:
130      items:
131        - description: format Default(0), I2S(1) or PDM(2)
132          enum: [0, 1, 2]
133        - description: dataline mask for 'rx'
134        - description: dataline mask for 'tx'
135
136  fsl,sai-mclk-direction-output:
137    description: SAI will output the SAI MCLK clock.
138    type: boolean
139
140  fsl,sai-synchronous-rx:
141    description: |
142      SAI will work in the synchronous mode (sync Tx with Rx) which means
143      both the transmitter and the receiver will send and receive data by
144      following receiver's bit clocks and frame sync clocks.
145    type: boolean
146
147  fsl,sai-asynchronous:
148    description: |
149      SAI will work in the asynchronous mode, which means both transmitter
150      and receiver will send and receive data by following their own bit clocks
151      and frame sync clocks separately.
152      If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
153      default synchronous mode (sync Rx with Tx) will be used, which means both
154      transmitter and receiver will send and receive data by following clocks
155      of transmitter.
156    type: boolean
157
158  fsl,shared-interrupt:
159    description: Interrupt is shared with other modules.
160    type: boolean
161
162  lsb-first:
163    description: |
164      Configures whether the LSB or the MSB is transmitted
165      first for the fifo data. If this property is absent,
166      the MSB is transmitted first as default, or the LSB
167      is transmitted first.
168    type: boolean
169
170  "#sound-dai-cells":
171    const: 0
172    description: optional, some dts node didn't add it.
173
174allOf:
175  - $ref: dai-common.yaml#
176  - if:
177      required:
178        - fsl,sai-asynchronous
179    then:
180      properties:
181        fsl,sai-synchronous-rx: false
182
183required:
184  - compatible
185  - reg
186  - clocks
187  - clock-names
188  - dmas
189  - dma-names
190  - interrupts
191
192unevaluatedProperties: false
193
194examples:
195  - |
196    #include <dt-bindings/interrupt-controller/arm-gic.h>
197    #include <dt-bindings/clock/vf610-clock.h>
198    sai2: sai@40031000 {
199        compatible = "fsl,vf610-sai";
200        reg = <0x40031000 0x1000>;
201        interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
202        pinctrl-names = "default";
203        pinctrl-0 = <&pinctrl_sai2_1>;
204        clocks = <&clks VF610_CLK_PLATFORM_BUS>,
205                 <&clks VF610_CLK_SAI2>,
206                 <&clks 0>, <&clks 0>;
207        clock-names = "bus", "mclk1", "mclk2", "mclk3";
208        dma-names = "rx", "tx";
209        dmas = <&edma0 0 20>, <&edma0 0 21>;
210        big-endian;
211        lsb-first;
212    };
213
214  - |
215    #include <dt-bindings/interrupt-controller/arm-gic.h>
216    #include <dt-bindings/clock/imx8mm-clock.h>
217    sai1: sai@30010000 {
218        compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
219        reg = <0x30010000 0x10000>;
220        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
221        clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
222                 <&clk IMX8MM_CLK_DUMMY>,
223                 <&clk IMX8MM_CLK_SAI1_ROOT>,
224                 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
225        clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
226        dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
227        dma-names = "rx", "tx";
228        fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
229        #sound-dai-cells = <0>;
230
231        ports {
232            #address-cells = <1>;
233            #size-cells = <0>;
234
235            port@1 {
236                reg = <1>;
237                playback-only;
238
239                sai1_endpoint0: endpoint {
240                   dai-tdm-slot-num = <8>;
241                   dai-tdm-slot-width = <32>;
242                   dai-tdm-slot-width-map = <32 8 32>;
243                   dai-format = "dsp_a";
244                   bitclock-master;
245                   frame-master;
246                   remote-endpoint = <&mcodec01_ep>;
247                };
248            };
249
250            port@2 {
251                reg = <2>;
252                capture-only;
253
254                sai1_endpoint1: endpoint {
255                    dai-tdm-slot-num = <8>;
256                    dai-tdm-slot-width = <32>;
257                    dai-tdm-slot-width-map = <32 8 32>;
258                    dai-format = "dsp_a";
259                    remote-endpoint = <&fe02_ep>;
260                };
261            };
262        };
263    };
264