19996cd78SChancel Liu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 29996cd78SChancel Liu%YAML 1.2 39996cd78SChancel Liu--- 49996cd78SChancel Liu$id: http://devicetree.org/schemas/sound/fsl,mqs.yaml# 59996cd78SChancel Liu$schema: http://devicetree.org/meta-schemas/core.yaml# 69996cd78SChancel Liu 79996cd78SChancel Liutitle: NXP Medium Quality Sound (MQS) 89996cd78SChancel Liu 99996cd78SChancel Liumaintainers: 109996cd78SChancel Liu - Shengjiu Wang <shengjiu.wang@nxp.com> 119996cd78SChancel Liu - Chancel Liu <chancel.liu@nxp.com> 129996cd78SChancel Liu 139996cd78SChancel Liudescription: | 149996cd78SChancel Liu Medium quality sound (MQS) is used to generate medium quality audio 159996cd78SChancel Liu via a standard GPIO in the pinmux, allowing the user to connect 169996cd78SChancel Liu stereo speakers or headphones to a power amplifier without an 179996cd78SChancel Liu additional DAC chip. 189996cd78SChancel Liu 199996cd78SChancel Liuproperties: 209996cd78SChancel Liu compatible: 219996cd78SChancel Liu enum: 229996cd78SChancel Liu - fsl,imx6sx-mqs 239996cd78SChancel Liu - fsl,imx8qm-mqs 249996cd78SChancel Liu - fsl,imx8qxp-mqs 259996cd78SChancel Liu - fsl,imx93-mqs 26*a1a771e5SShengjiu Wang - fsl,imx943-aonmix-mqs 27*a1a771e5SShengjiu Wang - fsl,imx943-wakeupmix-mqs 284c7d2dc6SShengjiu Wang - fsl,imx95-aonmix-mqs 294c7d2dc6SShengjiu Wang - fsl,imx95-netcmix-mqs 309996cd78SChancel Liu 319996cd78SChancel Liu clocks: 329996cd78SChancel Liu minItems: 1 339996cd78SChancel Liu maxItems: 2 349996cd78SChancel Liu 359996cd78SChancel Liu clock-names: 369996cd78SChancel Liu minItems: 1 379996cd78SChancel Liu maxItems: 2 389996cd78SChancel Liu 399996cd78SChancel Liu gpr: 409996cd78SChancel Liu $ref: /schemas/types.yaml#/definitions/phandle 419996cd78SChancel Liu description: The phandle to the General Purpose Register (GPR) node 429996cd78SChancel Liu 439996cd78SChancel Liu reg: 449996cd78SChancel Liu maxItems: 1 459996cd78SChancel Liu 469996cd78SChancel Liu power-domains: 479996cd78SChancel Liu maxItems: 1 489996cd78SChancel Liu 499996cd78SChancel Liu resets: 509996cd78SChancel Liu maxItems: 1 519996cd78SChancel Liu 529996cd78SChancel Liurequired: 539996cd78SChancel Liu - compatible 549996cd78SChancel Liu - clocks 559996cd78SChancel Liu - clock-names 569996cd78SChancel Liu 579996cd78SChancel LiuallOf: 589996cd78SChancel Liu - if: 599996cd78SChancel Liu properties: 609996cd78SChancel Liu compatible: 619996cd78SChancel Liu contains: 629996cd78SChancel Liu enum: 639996cd78SChancel Liu - fsl,imx8qm-mqs 649996cd78SChancel Liu - fsl,imx8qxp-mqs 659996cd78SChancel Liu then: 669996cd78SChancel Liu properties: 679996cd78SChancel Liu clocks: 689996cd78SChancel Liu items: 699996cd78SChancel Liu - description: Master clock 709996cd78SChancel Liu - description: Clock for register access 719996cd78SChancel Liu clock-names: 729996cd78SChancel Liu items: 739996cd78SChancel Liu - const: mclk 749996cd78SChancel Liu - const: core 759996cd78SChancel Liu required: 769996cd78SChancel Liu - reg 779996cd78SChancel Liu - power-domains 789996cd78SChancel Liu else: 799996cd78SChancel Liu properties: 809996cd78SChancel Liu clocks: 819996cd78SChancel Liu items: 829996cd78SChancel Liu - description: Master clock 839996cd78SChancel Liu clock-names: 849996cd78SChancel Liu items: 859996cd78SChancel Liu - const: mclk 869996cd78SChancel Liu required: 879996cd78SChancel Liu - gpr 889996cd78SChancel Liu 899996cd78SChancel LiuadditionalProperties: false 909996cd78SChancel Liu 919996cd78SChancel Liuexamples: 929996cd78SChancel Liu - | 939996cd78SChancel Liu #include <dt-bindings/clock/imx6sx-clock.h> 949996cd78SChancel Liu mqs0: mqs { 959996cd78SChancel Liu compatible = "fsl,imx6sx-mqs"; 969996cd78SChancel Liu gpr = <&gpr>; 979996cd78SChancel Liu clocks = <&clks IMX6SX_CLK_SAI1>; 989996cd78SChancel Liu clock-names = "mclk"; 999996cd78SChancel Liu }; 1009996cd78SChancel Liu 1019996cd78SChancel Liu - | 1029996cd78SChancel Liu #include <dt-bindings/firmware/imx/rsrc.h> 1039996cd78SChancel Liu mqs1: mqs@59850000 { 1049996cd78SChancel Liu compatible = "fsl,imx8qm-mqs"; 1059996cd78SChancel Liu reg = <0x59850000 0x10000>; 1069996cd78SChancel Liu clocks = <&mqs0_lpcg 0>, <&mqs0_lpcg 1>; 1079996cd78SChancel Liu clock-names = "mclk", "core"; 1089996cd78SChancel Liu power-domains = <&pd IMX_SC_R_MQS_0>; 1099996cd78SChancel Liu }; 110