xref: /linux/Documentation/devicetree/bindings/sound/fsl,sai.yaml (revision 58ae9a2aca6f883dd6fd7b8bfc2e1b1b21a2f03e)
1d5633368SShengjiu Wang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2d5633368SShengjiu Wang%YAML 1.2
3d5633368SShengjiu Wang---
4d5633368SShengjiu Wang$id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5d5633368SShengjiu Wang$schema: http://devicetree.org/meta-schemas/core.yaml#
6d5633368SShengjiu Wang
7d5633368SShengjiu Wangtitle: Freescale Synchronous Audio Interface (SAI).
8d5633368SShengjiu Wang
9d5633368SShengjiu Wangmaintainers:
10d5633368SShengjiu Wang  - Shengjiu Wang <shengjiu.wang@nxp.com>
11d5633368SShengjiu Wang
12d5633368SShengjiu Wangdescription: |
13d5633368SShengjiu Wang  The SAI is based on I2S module that used communicating with audio codecs,
14d5633368SShengjiu Wang  which provides a synchronous audio interface that supports fullduplex
15d5633368SShengjiu Wang  serial interfaces with frame synchronization such as I2S, AC97, TDM, and
16d5633368SShengjiu Wang  codec/DSP interfaces.
17d5633368SShengjiu Wang
18d5633368SShengjiu Wangproperties:
19d5633368SShengjiu Wang  compatible:
20d5633368SShengjiu Wang    oneOf:
2181b6c043SMarek Vasut      - items:
22d5633368SShengjiu Wang          - enum:
23d5633368SShengjiu Wang              - fsl,imx6ul-sai
2481b6c043SMarek Vasut              - fsl,imx7d-sai
2581b6c043SMarek Vasut          - const: fsl,imx6sx-sai
2681b6c043SMarek Vasut
27d5633368SShengjiu Wang      - items:
28d5633368SShengjiu Wang          - enum:
29d5633368SShengjiu Wang              - fsl,imx8mm-sai
30d5633368SShengjiu Wang              - fsl,imx8mn-sai
31d5633368SShengjiu Wang              - fsl,imx8mp-sai
32d5633368SShengjiu Wang          - const: fsl,imx8mq-sai
33d5633368SShengjiu Wang
3481b6c043SMarek Vasut      - items:
3581b6c043SMarek Vasut          - enum:
3681b6c043SMarek Vasut              - fsl,imx6sx-sai
3781b6c043SMarek Vasut              - fsl,imx7ulp-sai
3881b6c043SMarek Vasut              - fsl,imx8mq-sai
3981b6c043SMarek Vasut              - fsl,imx8qm-sai
4081b6c043SMarek Vasut              - fsl,imx8ulp-sai
4181b6c043SMarek Vasut              - fsl,vf610-sai
4281b6c043SMarek Vasut
43d5633368SShengjiu Wang  reg:
44d5633368SShengjiu Wang    maxItems: 1
45d5633368SShengjiu Wang
46d5633368SShengjiu Wang  clocks:
47d5633368SShengjiu Wang    items:
48d5633368SShengjiu Wang      - description: The ipg clock for register access
49d5633368SShengjiu Wang      - description: master clock source 0 (obsoleted)
50d5633368SShengjiu Wang      - description: master clock source 1
51d5633368SShengjiu Wang      - description: master clock source 2
52d5633368SShengjiu Wang      - description: master clock source 3
53d5633368SShengjiu Wang      - description: PLL clock source for 8kHz series
54d5633368SShengjiu Wang      - description: PLL clock source for 11kHz series
55d5633368SShengjiu Wang    minItems: 4
56d5633368SShengjiu Wang
57d5633368SShengjiu Wang  clock-names:
58d5633368SShengjiu Wang    oneOf:
59d5633368SShengjiu Wang      - items:
60d5633368SShengjiu Wang          - const: bus
61d5633368SShengjiu Wang          - const: mclk0
62d5633368SShengjiu Wang          - const: mclk1
63d5633368SShengjiu Wang          - const: mclk2
64d5633368SShengjiu Wang          - const: mclk3
65d5633368SShengjiu Wang          - const: pll8k
66d5633368SShengjiu Wang          - const: pll11k
67ef555955SMarek Vasut        minItems: 5
68d5633368SShengjiu Wang      - items:
69d5633368SShengjiu Wang          - const: bus
70d5633368SShengjiu Wang          - const: mclk1
71d5633368SShengjiu Wang          - const: mclk2
72d5633368SShengjiu Wang          - const: mclk3
73d5633368SShengjiu Wang          - const: pll8k
74d5633368SShengjiu Wang          - const: pll11k
75d5633368SShengjiu Wang        minItems: 4
76d5633368SShengjiu Wang
773e4f964dSMarek Vasut  dmas:
783e4f964dSMarek Vasut    maxItems: 2
793e4f964dSMarek Vasut
803e4f964dSMarek Vasut  dma-names:
813e4f964dSMarek Vasut    maxItems: 2
823e4f964dSMarek Vasut
833e4f964dSMarek Vasut  interrupts:
843e4f964dSMarek Vasut    items:
853e4f964dSMarek Vasut      - description: receive and transmit interrupt
86d5633368SShengjiu Wang
87d5633368SShengjiu Wang  big-endian:
88d5633368SShengjiu Wang    description: |
89d5633368SShengjiu Wang      required if all the SAI registers are big-endian rather than little-endian.
90d5633368SShengjiu Wang    type: boolean
91d5633368SShengjiu Wang
923e4f964dSMarek Vasut  fsl,dataline:
933e4f964dSMarek Vasut    $ref: /schemas/types.yaml#/definitions/uint32-matrix
943e4f964dSMarek Vasut    description: |
953e4f964dSMarek Vasut      Configure the dataline. It has 3 value for each configuration
963e4f964dSMarek Vasut    maxItems: 16
973e4f964dSMarek Vasut    items:
983e4f964dSMarek Vasut      items:
993e4f964dSMarek Vasut        - description: format Default(0), I2S(1) or PDM(2)
1003e4f964dSMarek Vasut          enum: [0, 1, 2]
1013e4f964dSMarek Vasut        - description: dataline mask for 'rx'
1023e4f964dSMarek Vasut        - description: dataline mask for 'tx'
1033e4f964dSMarek Vasut
1043e4f964dSMarek Vasut  fsl,sai-mclk-direction-output:
1053e4f964dSMarek Vasut    description: SAI will output the SAI MCLK clock.
1063e4f964dSMarek Vasut    type: boolean
1073e4f964dSMarek Vasut
108d5633368SShengjiu Wang  fsl,sai-synchronous-rx:
109d5633368SShengjiu Wang    description: |
110d5633368SShengjiu Wang      SAI will work in the synchronous mode (sync Tx with Rx) which means
111d5633368SShengjiu Wang      both the transmitter and the receiver will send and receive data by
112d5633368SShengjiu Wang      following receiver's bit clocks and frame sync clocks.
113d5633368SShengjiu Wang    type: boolean
114d5633368SShengjiu Wang
115d5633368SShengjiu Wang  fsl,sai-asynchronous:
116d5633368SShengjiu Wang    description: |
117d5633368SShengjiu Wang      SAI will work in the asynchronous mode, which means both transmitter
118d5633368SShengjiu Wang      and receiver will send and receive data by following their own bit clocks
119d5633368SShengjiu Wang      and frame sync clocks separately.
120d5633368SShengjiu Wang      If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
121d5633368SShengjiu Wang      default synchronous mode (sync Rx with Tx) will be used, which means both
122d5633368SShengjiu Wang      transmitter and receiver will send and receive data by following clocks
123d5633368SShengjiu Wang      of transmitter.
124d5633368SShengjiu Wang    type: boolean
125d5633368SShengjiu Wang
126d5633368SShengjiu Wang  fsl,shared-interrupt:
127d5633368SShengjiu Wang    description: Interrupt is shared with other modules.
128d5633368SShengjiu Wang    type: boolean
129d5633368SShengjiu Wang
1303e4f964dSMarek Vasut  lsb-first:
1313e4f964dSMarek Vasut    description: |
1323e4f964dSMarek Vasut      Configures whether the LSB or the MSB is transmitted
1333e4f964dSMarek Vasut      first for the fifo data. If this property is absent,
1343e4f964dSMarek Vasut      the MSB is transmitted first as default, or the LSB
1353e4f964dSMarek Vasut      is transmitted first.
1363e4f964dSMarek Vasut    type: boolean
1373e4f964dSMarek Vasut
138d5633368SShengjiu Wang  "#sound-dai-cells":
139d5633368SShengjiu Wang    const: 0
140d5633368SShengjiu Wang    description: optional, some dts node didn't add it.
141d5633368SShengjiu Wang
142d5633368SShengjiu WangallOf:
143*58ae9a2aSKrzysztof Kozlowski  - $ref: dai-common.yaml#
144d5633368SShengjiu Wang  - if:
145d5633368SShengjiu Wang      properties:
146d5633368SShengjiu Wang        compatible:
147d5633368SShengjiu Wang          contains:
148d5633368SShengjiu Wang            const: fsl,vf610-sai
149d5633368SShengjiu Wang    then:
150d5633368SShengjiu Wang      properties:
151d5633368SShengjiu Wang        dmas:
152d5633368SShengjiu Wang          items:
153d5633368SShengjiu Wang            - description: DMA controller phandle and request line for TX
154d5633368SShengjiu Wang            - description: DMA controller phandle and request line for RX
155d5633368SShengjiu Wang        dma-names:
156d5633368SShengjiu Wang          items:
157d5633368SShengjiu Wang            - const: tx
158d5633368SShengjiu Wang            - const: rx
159d5633368SShengjiu Wang    else:
160d5633368SShengjiu Wang      properties:
161d5633368SShengjiu Wang        dmas:
162d5633368SShengjiu Wang          items:
163d5633368SShengjiu Wang            - description: DMA controller phandle and request line for RX
164d5633368SShengjiu Wang            - description: DMA controller phandle and request line for TX
165d5633368SShengjiu Wang        dma-names:
166d5633368SShengjiu Wang          items:
167d5633368SShengjiu Wang            - const: rx
168d5633368SShengjiu Wang            - const: tx
169d5633368SShengjiu Wang  - if:
170d5633368SShengjiu Wang      required:
171d5633368SShengjiu Wang        - fsl,sai-asynchronous
172d5633368SShengjiu Wang    then:
173d5633368SShengjiu Wang      properties:
174d5633368SShengjiu Wang        fsl,sai-synchronous-rx: false
175d5633368SShengjiu Wang
176d5633368SShengjiu Wangrequired:
177d5633368SShengjiu Wang  - compatible
178d5633368SShengjiu Wang  - reg
179d5633368SShengjiu Wang  - clocks
180d5633368SShengjiu Wang  - clock-names
1813e4f964dSMarek Vasut  - dmas
1823e4f964dSMarek Vasut  - dma-names
1833e4f964dSMarek Vasut  - interrupts
184d5633368SShengjiu Wang
185*58ae9a2aSKrzysztof KozlowskiunevaluatedProperties: false
186d5633368SShengjiu Wang
187d5633368SShengjiu Wangexamples:
188d5633368SShengjiu Wang  - |
189d5633368SShengjiu Wang    #include <dt-bindings/interrupt-controller/arm-gic.h>
190d5633368SShengjiu Wang    #include <dt-bindings/clock/vf610-clock.h>
191d5633368SShengjiu Wang    sai2: sai@40031000 {
192d5633368SShengjiu Wang        compatible = "fsl,vf610-sai";
193d5633368SShengjiu Wang        reg = <0x40031000 0x1000>;
194d5633368SShengjiu Wang        interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
195d5633368SShengjiu Wang        pinctrl-names = "default";
196d5633368SShengjiu Wang        pinctrl-0 = <&pinctrl_sai2_1>;
197d5633368SShengjiu Wang        clocks = <&clks VF610_CLK_PLATFORM_BUS>,
198d5633368SShengjiu Wang                 <&clks VF610_CLK_SAI2>,
199d5633368SShengjiu Wang                 <&clks 0>, <&clks 0>;
200d5633368SShengjiu Wang        clock-names = "bus", "mclk1", "mclk2", "mclk3";
201d5633368SShengjiu Wang        dma-names = "tx", "rx";
202d5633368SShengjiu Wang        dmas = <&edma0 0 21>,
203d5633368SShengjiu Wang               <&edma0 0 20>;
204d5633368SShengjiu Wang        big-endian;
205d5633368SShengjiu Wang        lsb-first;
206d5633368SShengjiu Wang    };
207d5633368SShengjiu Wang
208d5633368SShengjiu Wang  - |
209d5633368SShengjiu Wang    #include <dt-bindings/interrupt-controller/arm-gic.h>
210d5633368SShengjiu Wang    #include <dt-bindings/clock/imx8mm-clock.h>
211d5633368SShengjiu Wang    sai1: sai@30010000 {
212d5633368SShengjiu Wang        compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
213d5633368SShengjiu Wang        reg = <0x30010000 0x10000>;
214d5633368SShengjiu Wang        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
215d5633368SShengjiu Wang        clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
216d5633368SShengjiu Wang                 <&clk IMX8MM_CLK_DUMMY>,
217d5633368SShengjiu Wang                 <&clk IMX8MM_CLK_SAI1_ROOT>,
218d5633368SShengjiu Wang                 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
219d5633368SShengjiu Wang        clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
220d5633368SShengjiu Wang        dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
221d5633368SShengjiu Wang        dma-names = "rx", "tx";
222d5633368SShengjiu Wang        fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
223d5633368SShengjiu Wang        #sound-dai-cells = <0>;
224d5633368SShengjiu Wang    };
225