xref: /linux/Documentation/devicetree/bindings/sound/fsl,sai.yaml (revision 52523f70fdf9b2cb0bfd1999eba4aa3a30b04fa6)
1d5633368SShengjiu Wang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2d5633368SShengjiu Wang%YAML 1.2
3d5633368SShengjiu Wang---
4d5633368SShengjiu Wang$id: http://devicetree.org/schemas/sound/fsl,sai.yaml#
5d5633368SShengjiu Wang$schema: http://devicetree.org/meta-schemas/core.yaml#
6d5633368SShengjiu Wang
7d5633368SShengjiu Wangtitle: Freescale Synchronous Audio Interface (SAI).
8d5633368SShengjiu Wang
9d5633368SShengjiu Wangmaintainers:
10d5633368SShengjiu Wang  - Shengjiu Wang <shengjiu.wang@nxp.com>
11d5633368SShengjiu Wang
12d5633368SShengjiu Wangdescription: |
13d5633368SShengjiu Wang  The SAI is based on I2S module that used communicating with audio codecs,
14d5633368SShengjiu Wang  which provides a synchronous audio interface that supports fullduplex
15d5633368SShengjiu Wang  serial interfaces with frame synchronization such as I2S, AC97, TDM, and
16d5633368SShengjiu Wang  codec/DSP interfaces.
17d5633368SShengjiu Wang
18d5633368SShengjiu Wangproperties:
19d5633368SShengjiu Wang  compatible:
20d5633368SShengjiu Wang    oneOf:
2181b6c043SMarek Vasut      - items:
22d5633368SShengjiu Wang          - enum:
23d5633368SShengjiu Wang              - fsl,imx6ul-sai
2481b6c043SMarek Vasut              - fsl,imx7d-sai
2581b6c043SMarek Vasut          - const: fsl,imx6sx-sai
2681b6c043SMarek Vasut
27d5633368SShengjiu Wang      - items:
28d5633368SShengjiu Wang          - enum:
29d5633368SShengjiu Wang              - fsl,imx8mm-sai
30d5633368SShengjiu Wang              - fsl,imx8mn-sai
31d5633368SShengjiu Wang              - fsl,imx8mp-sai
32d5633368SShengjiu Wang          - const: fsl,imx8mq-sai
33d5633368SShengjiu Wang
3481b6c043SMarek Vasut      - items:
3581b6c043SMarek Vasut          - enum:
3681b6c043SMarek Vasut              - fsl,imx6sx-sai
3781b6c043SMarek Vasut              - fsl,imx7ulp-sai
3881b6c043SMarek Vasut              - fsl,imx8mq-sai
3981b6c043SMarek Vasut              - fsl,imx8qm-sai
4081b6c043SMarek Vasut              - fsl,imx8ulp-sai
41e85b1f5aSMarek Vasut              - fsl,imx93-sai
42*52523f70SChancel Liu              - fsl,imx95-sai
4381b6c043SMarek Vasut              - fsl,vf610-sai
4481b6c043SMarek Vasut
45d5633368SShengjiu Wang  reg:
46d5633368SShengjiu Wang    maxItems: 1
47d5633368SShengjiu Wang
48d5633368SShengjiu Wang  clocks:
49d5633368SShengjiu Wang    items:
50d5633368SShengjiu Wang      - description: The ipg clock for register access
51d5633368SShengjiu Wang      - description: master clock source 0 (obsoleted)
52d5633368SShengjiu Wang      - description: master clock source 1
53d5633368SShengjiu Wang      - description: master clock source 2
54d5633368SShengjiu Wang      - description: master clock source 3
55d5633368SShengjiu Wang      - description: PLL clock source for 8kHz series
56d5633368SShengjiu Wang      - description: PLL clock source for 11kHz series
57d5633368SShengjiu Wang    minItems: 4
58d5633368SShengjiu Wang
59d5633368SShengjiu Wang  clock-names:
60d5633368SShengjiu Wang    oneOf:
61d5633368SShengjiu Wang      - items:
62d5633368SShengjiu Wang          - const: bus
63d5633368SShengjiu Wang          - const: mclk0
64d5633368SShengjiu Wang          - const: mclk1
65d5633368SShengjiu Wang          - const: mclk2
66d5633368SShengjiu Wang          - const: mclk3
67d5633368SShengjiu Wang          - const: pll8k
68d5633368SShengjiu Wang          - const: pll11k
69ef555955SMarek Vasut        minItems: 5
70d5633368SShengjiu Wang      - items:
71d5633368SShengjiu Wang          - const: bus
72d5633368SShengjiu Wang          - const: mclk1
73d5633368SShengjiu Wang          - const: mclk2
74d5633368SShengjiu Wang          - const: mclk3
75d5633368SShengjiu Wang          - const: pll8k
76d5633368SShengjiu Wang          - const: pll11k
77d5633368SShengjiu Wang        minItems: 4
78d5633368SShengjiu Wang
793e4f964dSMarek Vasut  dmas:
8021d64f6fSMarek Vasut    items:
8121d64f6fSMarek Vasut      - description: DMA controller phandle and request line for RX
8221d64f6fSMarek Vasut      - description: DMA controller phandle and request line for TX
833e4f964dSMarek Vasut
843e4f964dSMarek Vasut  dma-names:
8521d64f6fSMarek Vasut    items:
8621d64f6fSMarek Vasut      - const: rx
8721d64f6fSMarek Vasut      - const: tx
883e4f964dSMarek Vasut
893e4f964dSMarek Vasut  interrupts:
903e4f964dSMarek Vasut    items:
913e4f964dSMarek Vasut      - description: receive and transmit interrupt
92d5633368SShengjiu Wang
93d5633368SShengjiu Wang  big-endian:
94d5633368SShengjiu Wang    description: |
95d5633368SShengjiu Wang      required if all the SAI registers are big-endian rather than little-endian.
96d5633368SShengjiu Wang    type: boolean
97d5633368SShengjiu Wang
983e4f964dSMarek Vasut  fsl,dataline:
993e4f964dSMarek Vasut    $ref: /schemas/types.yaml#/definitions/uint32-matrix
1003e4f964dSMarek Vasut    description: |
1013e4f964dSMarek Vasut      Configure the dataline. It has 3 value for each configuration
1023e4f964dSMarek Vasut    maxItems: 16
1033e4f964dSMarek Vasut    items:
1043e4f964dSMarek Vasut      items:
1053e4f964dSMarek Vasut        - description: format Default(0), I2S(1) or PDM(2)
1063e4f964dSMarek Vasut          enum: [0, 1, 2]
1073e4f964dSMarek Vasut        - description: dataline mask for 'rx'
1083e4f964dSMarek Vasut        - description: dataline mask for 'tx'
1093e4f964dSMarek Vasut
1103e4f964dSMarek Vasut  fsl,sai-mclk-direction-output:
1113e4f964dSMarek Vasut    description: SAI will output the SAI MCLK clock.
1123e4f964dSMarek Vasut    type: boolean
1133e4f964dSMarek Vasut
114d5633368SShengjiu Wang  fsl,sai-synchronous-rx:
115d5633368SShengjiu Wang    description: |
116d5633368SShengjiu Wang      SAI will work in the synchronous mode (sync Tx with Rx) which means
117d5633368SShengjiu Wang      both the transmitter and the receiver will send and receive data by
118d5633368SShengjiu Wang      following receiver's bit clocks and frame sync clocks.
119d5633368SShengjiu Wang    type: boolean
120d5633368SShengjiu Wang
121d5633368SShengjiu Wang  fsl,sai-asynchronous:
122d5633368SShengjiu Wang    description: |
123d5633368SShengjiu Wang      SAI will work in the asynchronous mode, which means both transmitter
124d5633368SShengjiu Wang      and receiver will send and receive data by following their own bit clocks
125d5633368SShengjiu Wang      and frame sync clocks separately.
126d5633368SShengjiu Wang      If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
127d5633368SShengjiu Wang      default synchronous mode (sync Rx with Tx) will be used, which means both
128d5633368SShengjiu Wang      transmitter and receiver will send and receive data by following clocks
129d5633368SShengjiu Wang      of transmitter.
130d5633368SShengjiu Wang    type: boolean
131d5633368SShengjiu Wang
132d5633368SShengjiu Wang  fsl,shared-interrupt:
133d5633368SShengjiu Wang    description: Interrupt is shared with other modules.
134d5633368SShengjiu Wang    type: boolean
135d5633368SShengjiu Wang
1363e4f964dSMarek Vasut  lsb-first:
1373e4f964dSMarek Vasut    description: |
1383e4f964dSMarek Vasut      Configures whether the LSB or the MSB is transmitted
1393e4f964dSMarek Vasut      first for the fifo data. If this property is absent,
1403e4f964dSMarek Vasut      the MSB is transmitted first as default, or the LSB
1413e4f964dSMarek Vasut      is transmitted first.
1423e4f964dSMarek Vasut    type: boolean
1433e4f964dSMarek Vasut
144d5633368SShengjiu Wang  "#sound-dai-cells":
145d5633368SShengjiu Wang    const: 0
146d5633368SShengjiu Wang    description: optional, some dts node didn't add it.
147d5633368SShengjiu Wang
148d5633368SShengjiu WangallOf:
14958ae9a2aSKrzysztof Kozlowski  - $ref: dai-common.yaml#
150d5633368SShengjiu Wang  - if:
151d5633368SShengjiu Wang      required:
152d5633368SShengjiu Wang        - fsl,sai-asynchronous
153d5633368SShengjiu Wang    then:
154d5633368SShengjiu Wang      properties:
155d5633368SShengjiu Wang        fsl,sai-synchronous-rx: false
156d5633368SShengjiu Wang
157d5633368SShengjiu Wangrequired:
158d5633368SShengjiu Wang  - compatible
159d5633368SShengjiu Wang  - reg
160d5633368SShengjiu Wang  - clocks
161d5633368SShengjiu Wang  - clock-names
1623e4f964dSMarek Vasut  - dmas
1633e4f964dSMarek Vasut  - dma-names
1643e4f964dSMarek Vasut  - interrupts
165d5633368SShengjiu Wang
16658ae9a2aSKrzysztof KozlowskiunevaluatedProperties: false
167d5633368SShengjiu Wang
168d5633368SShengjiu Wangexamples:
169d5633368SShengjiu Wang  - |
170d5633368SShengjiu Wang    #include <dt-bindings/interrupt-controller/arm-gic.h>
171d5633368SShengjiu Wang    #include <dt-bindings/clock/vf610-clock.h>
172d5633368SShengjiu Wang    sai2: sai@40031000 {
173d5633368SShengjiu Wang        compatible = "fsl,vf610-sai";
174d5633368SShengjiu Wang        reg = <0x40031000 0x1000>;
175d5633368SShengjiu Wang        interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
176d5633368SShengjiu Wang        pinctrl-names = "default";
177d5633368SShengjiu Wang        pinctrl-0 = <&pinctrl_sai2_1>;
178d5633368SShengjiu Wang        clocks = <&clks VF610_CLK_PLATFORM_BUS>,
179d5633368SShengjiu Wang                 <&clks VF610_CLK_SAI2>,
180d5633368SShengjiu Wang                 <&clks 0>, <&clks 0>;
181d5633368SShengjiu Wang        clock-names = "bus", "mclk1", "mclk2", "mclk3";
18221d64f6fSMarek Vasut        dma-names = "rx", "tx";
18321d64f6fSMarek Vasut        dmas = <&edma0 0 20>, <&edma0 0 21>;
184d5633368SShengjiu Wang        big-endian;
185d5633368SShengjiu Wang        lsb-first;
186d5633368SShengjiu Wang    };
187d5633368SShengjiu Wang
188d5633368SShengjiu Wang  - |
189d5633368SShengjiu Wang    #include <dt-bindings/interrupt-controller/arm-gic.h>
190d5633368SShengjiu Wang    #include <dt-bindings/clock/imx8mm-clock.h>
191d5633368SShengjiu Wang    sai1: sai@30010000 {
192d5633368SShengjiu Wang        compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
193d5633368SShengjiu Wang        reg = <0x30010000 0x10000>;
194d5633368SShengjiu Wang        interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
195d5633368SShengjiu Wang        clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
196d5633368SShengjiu Wang                 <&clk IMX8MM_CLK_DUMMY>,
197d5633368SShengjiu Wang                 <&clk IMX8MM_CLK_SAI1_ROOT>,
198d5633368SShengjiu Wang                 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
199d5633368SShengjiu Wang        clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
200d5633368SShengjiu Wang        dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
201d5633368SShengjiu Wang        dma-names = "rx", "tx";
202d5633368SShengjiu Wang        fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
203d5633368SShengjiu Wang        #sound-dai-cells = <0>;
204d5633368SShengjiu Wang    };
205