1*9996cd78SChancel Liu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*9996cd78SChancel Liu%YAML 1.2 3*9996cd78SChancel Liu--- 4*9996cd78SChancel Liu$id: http://devicetree.org/schemas/sound/fsl,mqs.yaml# 5*9996cd78SChancel Liu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*9996cd78SChancel Liu 7*9996cd78SChancel Liutitle: NXP Medium Quality Sound (MQS) 8*9996cd78SChancel Liu 9*9996cd78SChancel Liumaintainers: 10*9996cd78SChancel Liu - Shengjiu Wang <shengjiu.wang@nxp.com> 11*9996cd78SChancel Liu - Chancel Liu <chancel.liu@nxp.com> 12*9996cd78SChancel Liu 13*9996cd78SChancel Liudescription: | 14*9996cd78SChancel Liu Medium quality sound (MQS) is used to generate medium quality audio 15*9996cd78SChancel Liu via a standard GPIO in the pinmux, allowing the user to connect 16*9996cd78SChancel Liu stereo speakers or headphones to a power amplifier without an 17*9996cd78SChancel Liu additional DAC chip. 18*9996cd78SChancel Liu 19*9996cd78SChancel Liuproperties: 20*9996cd78SChancel Liu compatible: 21*9996cd78SChancel Liu enum: 22*9996cd78SChancel Liu - fsl,imx6sx-mqs 23*9996cd78SChancel Liu - fsl,imx8qm-mqs 24*9996cd78SChancel Liu - fsl,imx8qxp-mqs 25*9996cd78SChancel Liu - fsl,imx93-mqs 26*9996cd78SChancel Liu 27*9996cd78SChancel Liu clocks: 28*9996cd78SChancel Liu minItems: 1 29*9996cd78SChancel Liu maxItems: 2 30*9996cd78SChancel Liu 31*9996cd78SChancel Liu clock-names: 32*9996cd78SChancel Liu minItems: 1 33*9996cd78SChancel Liu maxItems: 2 34*9996cd78SChancel Liu 35*9996cd78SChancel Liu gpr: 36*9996cd78SChancel Liu $ref: /schemas/types.yaml#/definitions/phandle 37*9996cd78SChancel Liu description: The phandle to the General Purpose Register (GPR) node 38*9996cd78SChancel Liu 39*9996cd78SChancel Liu reg: 40*9996cd78SChancel Liu maxItems: 1 41*9996cd78SChancel Liu 42*9996cd78SChancel Liu power-domains: 43*9996cd78SChancel Liu maxItems: 1 44*9996cd78SChancel Liu 45*9996cd78SChancel Liu resets: 46*9996cd78SChancel Liu maxItems: 1 47*9996cd78SChancel Liu 48*9996cd78SChancel Liurequired: 49*9996cd78SChancel Liu - compatible 50*9996cd78SChancel Liu - clocks 51*9996cd78SChancel Liu - clock-names 52*9996cd78SChancel Liu 53*9996cd78SChancel LiuallOf: 54*9996cd78SChancel Liu - if: 55*9996cd78SChancel Liu properties: 56*9996cd78SChancel Liu compatible: 57*9996cd78SChancel Liu contains: 58*9996cd78SChancel Liu enum: 59*9996cd78SChancel Liu - fsl,imx8qm-mqs 60*9996cd78SChancel Liu - fsl,imx8qxp-mqs 61*9996cd78SChancel Liu then: 62*9996cd78SChancel Liu properties: 63*9996cd78SChancel Liu clocks: 64*9996cd78SChancel Liu items: 65*9996cd78SChancel Liu - description: Master clock 66*9996cd78SChancel Liu - description: Clock for register access 67*9996cd78SChancel Liu clock-names: 68*9996cd78SChancel Liu items: 69*9996cd78SChancel Liu - const: mclk 70*9996cd78SChancel Liu - const: core 71*9996cd78SChancel Liu required: 72*9996cd78SChancel Liu - reg 73*9996cd78SChancel Liu - power-domains 74*9996cd78SChancel Liu else: 75*9996cd78SChancel Liu properties: 76*9996cd78SChancel Liu clocks: 77*9996cd78SChancel Liu items: 78*9996cd78SChancel Liu - description: Master clock 79*9996cd78SChancel Liu clock-names: 80*9996cd78SChancel Liu items: 81*9996cd78SChancel Liu - const: mclk 82*9996cd78SChancel Liu required: 83*9996cd78SChancel Liu - gpr 84*9996cd78SChancel Liu 85*9996cd78SChancel LiuadditionalProperties: false 86*9996cd78SChancel Liu 87*9996cd78SChancel Liuexamples: 88*9996cd78SChancel Liu - | 89*9996cd78SChancel Liu #include <dt-bindings/clock/imx6sx-clock.h> 90*9996cd78SChancel Liu mqs0: mqs { 91*9996cd78SChancel Liu compatible = "fsl,imx6sx-mqs"; 92*9996cd78SChancel Liu gpr = <&gpr>; 93*9996cd78SChancel Liu clocks = <&clks IMX6SX_CLK_SAI1>; 94*9996cd78SChancel Liu clock-names = "mclk"; 95*9996cd78SChancel Liu }; 96*9996cd78SChancel Liu 97*9996cd78SChancel Liu - | 98*9996cd78SChancel Liu #include <dt-bindings/firmware/imx/rsrc.h> 99*9996cd78SChancel Liu mqs1: mqs@59850000 { 100*9996cd78SChancel Liu compatible = "fsl,imx8qm-mqs"; 101*9996cd78SChancel Liu reg = <0x59850000 0x10000>; 102*9996cd78SChancel Liu clocks = <&mqs0_lpcg 0>, <&mqs0_lpcg 1>; 103*9996cd78SChancel Liu clock-names = "mclk", "core"; 104*9996cd78SChancel Liu power-domains = <&pd IMX_SC_R_MQS_0>; 105*9996cd78SChancel Liu }; 106