102d91fe4SShengjiu Wang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 202d91fe4SShengjiu Wang%YAML 1.2 302d91fe4SShengjiu Wang--- 402d91fe4SShengjiu Wang$id: http://devicetree.org/schemas/sound/fsl,micfil.yaml# 502d91fe4SShengjiu Wang$schema: http://devicetree.org/meta-schemas/core.yaml# 602d91fe4SShengjiu Wang 702d91fe4SShengjiu Wangtitle: NXP MICFIL Digital Audio Interface (MICFIL) 802d91fe4SShengjiu Wang 902d91fe4SShengjiu Wangmaintainers: 1002d91fe4SShengjiu Wang - Shengjiu Wang <shengjiu.wang@nxp.com> 1102d91fe4SShengjiu Wang 1202d91fe4SShengjiu Wangdescription: | 1302d91fe4SShengjiu Wang The MICFIL digital interface provides a 16-bit or 24-bit audio signal 1402d91fe4SShengjiu Wang from a PDM microphone bitstream in a configurable output sampling rate. 1502d91fe4SShengjiu Wang 1602d91fe4SShengjiu Wangproperties: 1702d91fe4SShengjiu Wang compatible: 18*20d27199SChancel Liu oneOf: 19*20d27199SChancel Liu - items: 20*20d27199SChancel Liu - enum: 21*20d27199SChancel Liu - fsl,imx95-micfil 22*20d27199SChancel Liu - const: fsl,imx93-micfil 23*20d27199SChancel Liu 24*20d27199SChancel Liu - enum: 2502d91fe4SShengjiu Wang - fsl,imx8mm-micfil 2602d91fe4SShengjiu Wang - fsl,imx8mp-micfil 27fb342568SChancel Liu - fsl,imx93-micfil 2802d91fe4SShengjiu Wang 2902d91fe4SShengjiu Wang reg: 3002d91fe4SShengjiu Wang maxItems: 1 3102d91fe4SShengjiu Wang 3202d91fe4SShengjiu Wang interrupts: 3302d91fe4SShengjiu Wang items: 3402d91fe4SShengjiu Wang - description: Digital Microphone interface interrupt 3502d91fe4SShengjiu Wang - description: Digital Microphone interface error interrupt 3602d91fe4SShengjiu Wang - description: voice activity detector event interrupt 3702d91fe4SShengjiu Wang - description: voice activity detector error interrupt 3802d91fe4SShengjiu Wang 3902d91fe4SShengjiu Wang dmas: 4002d91fe4SShengjiu Wang items: 4102d91fe4SShengjiu Wang - description: DMA controller phandle and request line for RX 4202d91fe4SShengjiu Wang 4302d91fe4SShengjiu Wang dma-names: 4402d91fe4SShengjiu Wang items: 4502d91fe4SShengjiu Wang - const: rx 4602d91fe4SShengjiu Wang 4702d91fe4SShengjiu Wang clocks: 4802d91fe4SShengjiu Wang items: 4902d91fe4SShengjiu Wang - description: The ipg clock for register access 5002d91fe4SShengjiu Wang - description: internal micfil clock 5102d91fe4SShengjiu Wang - description: PLL clock source for 8kHz series 5202d91fe4SShengjiu Wang - description: PLL clock source for 11kHz series 5302d91fe4SShengjiu Wang - description: External clock 3 5402d91fe4SShengjiu Wang minItems: 2 5502d91fe4SShengjiu Wang 5602d91fe4SShengjiu Wang clock-names: 5702d91fe4SShengjiu Wang items: 5802d91fe4SShengjiu Wang - const: ipg_clk 5902d91fe4SShengjiu Wang - const: ipg_clk_app 6002d91fe4SShengjiu Wang - const: pll8k 6102d91fe4SShengjiu Wang - const: pll11k 6202d91fe4SShengjiu Wang - const: clkext3 6302d91fe4SShengjiu Wang minItems: 2 6402d91fe4SShengjiu Wang 651426b9baSFabio Estevam "#sound-dai-cells": 661426b9baSFabio Estevam const: 0 671426b9baSFabio Estevam 6802d91fe4SShengjiu Wangrequired: 6902d91fe4SShengjiu Wang - compatible 7002d91fe4SShengjiu Wang - reg 7102d91fe4SShengjiu Wang - interrupts 7202d91fe4SShengjiu Wang - dmas 7302d91fe4SShengjiu Wang - dma-names 7402d91fe4SShengjiu Wang - clocks 7502d91fe4SShengjiu Wang - clock-names 7602d91fe4SShengjiu Wang 7702d91fe4SShengjiu WangadditionalProperties: false 7802d91fe4SShengjiu Wang 7902d91fe4SShengjiu Wangexamples: 8002d91fe4SShengjiu Wang - | 8102d91fe4SShengjiu Wang #include <dt-bindings/interrupt-controller/arm-gic.h> 8202d91fe4SShengjiu Wang #include <dt-bindings/clock/imx8mm-clock.h> 8302d91fe4SShengjiu Wang micfil: audio-controller@30080000 { 8402d91fe4SShengjiu Wang compatible = "fsl,imx8mm-micfil"; 8502d91fe4SShengjiu Wang reg = <0x30080000 0x10000>; 8602d91fe4SShengjiu Wang interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 8702d91fe4SShengjiu Wang <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 8802d91fe4SShengjiu Wang <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 8902d91fe4SShengjiu Wang <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 9002d91fe4SShengjiu Wang clocks = <&clk IMX8MM_CLK_PDM_IPG>, 9102d91fe4SShengjiu Wang <&clk IMX8MM_CLK_PDM_ROOT>; 9202d91fe4SShengjiu Wang clock-names = "ipg_clk", "ipg_clk_app"; 9302d91fe4SShengjiu Wang dmas = <&sdma2 24 25 0>; 9402d91fe4SShengjiu Wang dma-names = "rx"; 9502d91fe4SShengjiu Wang }; 96