1*7817eb1aSNikita Shubin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*7817eb1aSNikita Shubin%YAML 1.2 3*7817eb1aSNikita Shubin--- 4*7817eb1aSNikita Shubin$id: http://devicetree.org/schemas/sound/cirrus,cs4271.yaml# 5*7817eb1aSNikita Shubin$schema: http://devicetree.org/meta-schemas/core.yaml# 6*7817eb1aSNikita Shubin 7*7817eb1aSNikita Shubintitle: Cirrus Logic CS4271 audio CODEC 8*7817eb1aSNikita Shubin 9*7817eb1aSNikita Shubinmaintainers: 10*7817eb1aSNikita Shubin - Alexander Sverdlin <alexander.sverdlin@gmail.com> 11*7817eb1aSNikita Shubin - Nikita Shubin <nikita.shubin@maquefel.me> 12*7817eb1aSNikita Shubin 13*7817eb1aSNikita Shubindescription: 14*7817eb1aSNikita Shubin The CS4271 is a stereo audio codec. This device supports both the I2C 15*7817eb1aSNikita Shubin and the SPI bus. 16*7817eb1aSNikita Shubin 17*7817eb1aSNikita ShubinallOf: 18*7817eb1aSNikita Shubin - $ref: dai-common.yaml# 19*7817eb1aSNikita Shubin - $ref: /schemas/spi/spi-peripheral-props.yaml# 20*7817eb1aSNikita Shubin 21*7817eb1aSNikita Shubinproperties: 22*7817eb1aSNikita Shubin compatible: 23*7817eb1aSNikita Shubin const: cirrus,cs4271 24*7817eb1aSNikita Shubin 25*7817eb1aSNikita Shubin reg: 26*7817eb1aSNikita Shubin maxItems: 1 27*7817eb1aSNikita Shubin 28*7817eb1aSNikita Shubin spi-cpha: true 29*7817eb1aSNikita Shubin 30*7817eb1aSNikita Shubin spi-cpol: true 31*7817eb1aSNikita Shubin 32*7817eb1aSNikita Shubin '#sound-dai-cells': 33*7817eb1aSNikita Shubin const: 0 34*7817eb1aSNikita Shubin 35*7817eb1aSNikita Shubin reset-gpios: 36*7817eb1aSNikita Shubin description: 37*7817eb1aSNikita Shubin This pin will be deasserted before communication to the codec starts. 38*7817eb1aSNikita Shubin maxItems: 1 39*7817eb1aSNikita Shubin 40*7817eb1aSNikita Shubin va-supply: 41*7817eb1aSNikita Shubin description: Analog power supply. 42*7817eb1aSNikita Shubin 43*7817eb1aSNikita Shubin vd-supply: 44*7817eb1aSNikita Shubin description: Digital power supply. 45*7817eb1aSNikita Shubin 46*7817eb1aSNikita Shubin vl-supply: 47*7817eb1aSNikita Shubin description: Serial Control Port power supply. 48*7817eb1aSNikita Shubin 49*7817eb1aSNikita Shubin port: 50*7817eb1aSNikita Shubin $ref: audio-graph-port.yaml# 51*7817eb1aSNikita Shubin unevaluatedProperties: false 52*7817eb1aSNikita Shubin 53*7817eb1aSNikita Shubin cirrus,amuteb-eq-bmutec: 54*7817eb1aSNikita Shubin description: 55*7817eb1aSNikita Shubin When given, the Codec's AMUTEB=BMUTEC flag is enabled. 56*7817eb1aSNikita Shubin type: boolean 57*7817eb1aSNikita Shubin 58*7817eb1aSNikita Shubin cirrus,enable-soft-reset: 59*7817eb1aSNikita Shubin description: | 60*7817eb1aSNikita Shubin The CS4271 requires its LRCLK and MCLK to be stable before its RESET 61*7817eb1aSNikita Shubin line is de-asserted. That also means that clocks cannot be changed 62*7817eb1aSNikita Shubin without putting the chip back into hardware reset, which also requires 63*7817eb1aSNikita Shubin a complete re-initialization of all registers. 64*7817eb1aSNikita Shubin 65*7817eb1aSNikita Shubin One (undocumented) workaround is to assert and de-assert the PDN bit 66*7817eb1aSNikita Shubin in the MODE2 register. This workaround can be enabled with this DT 67*7817eb1aSNikita Shubin property. 68*7817eb1aSNikita Shubin 69*7817eb1aSNikita Shubin Note that this is not needed in case the clocks are stable 70*7817eb1aSNikita Shubin throughout the entire runtime of the codec. 71*7817eb1aSNikita Shubin type: boolean 72*7817eb1aSNikita Shubin 73*7817eb1aSNikita Shubinrequired: 74*7817eb1aSNikita Shubin - compatible 75*7817eb1aSNikita Shubin - reg 76*7817eb1aSNikita Shubin 77*7817eb1aSNikita ShubinunevaluatedProperties: false 78*7817eb1aSNikita Shubin 79*7817eb1aSNikita Shubinexamples: 80*7817eb1aSNikita Shubin - | 81*7817eb1aSNikita Shubin #include <dt-bindings/gpio/gpio.h> 82*7817eb1aSNikita Shubin spi { 83*7817eb1aSNikita Shubin #address-cells = <1>; 84*7817eb1aSNikita Shubin #size-cells = <0>; 85*7817eb1aSNikita Shubin codec@0 { 86*7817eb1aSNikita Shubin compatible = "cirrus,cs4271"; 87*7817eb1aSNikita Shubin reg = <0>; 88*7817eb1aSNikita Shubin #sound-dai-cells = <0>; 89*7817eb1aSNikita Shubin spi-max-frequency = <6000000>; 90*7817eb1aSNikita Shubin spi-cpol; 91*7817eb1aSNikita Shubin spi-cpha; 92*7817eb1aSNikita Shubin reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; 93*7817eb1aSNikita Shubin port { 94*7817eb1aSNikita Shubin endpoint { 95*7817eb1aSNikita Shubin remote-endpoint = <&i2s_ep>; 96*7817eb1aSNikita Shubin }; 97*7817eb1aSNikita Shubin }; 98*7817eb1aSNikita Shubin }; 99*7817eb1aSNikita Shubin }; 100*7817eb1aSNikita Shubin 101*7817eb1aSNikita Shubin... 102