1LogicoreIP designed compatible with Xilinx ZYNQ family. 2------------------------------------------------------- 3 4General concept 5--------------- 6 7LogicoreIP design to provide the isolation between processing system 8and programmable logic. Also provides the list of register set to configure 9the frequency. 10 11Required properties: 12- compatible: shall be one of: 13 "xlnx,vcu" 14 "xlnx,vcu-logicoreip-1.0" 15- reg, reg-names: There are two sets of registers need to provide. 16 1. vcu slcr 17 2. Logicore 18 reg-names should contain name for the each register sequence. 19- clocks: phandle for aclk and pll_ref clocksource 20- clock-names: The identification string, "aclk", is always required for 21 the axi clock. "pll_ref" is required for pll. 22Example: 23 24 xlnx_vcu: vcu@a0040000 { 25 compatible = "xlnx,vcu-logicoreip-1.0"; 26 reg = <0x0 0xa0040000 0x0 0x1000>, 27 <0x0 0xa0041000 0x0 0x1000>; 28 reg-names = "vcu_slcr", "logicore"; 29 clocks = <&si570_1>, <&clkc 71>; 30 clock-names = "pll_ref", "aclk"; 31 }; 32