xref: /linux/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml (revision ae22a94997b8a03dcb3c922857c203246711f9d4) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/qcom/qcom,smsm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Shared Memory State Machine
8
9maintainers:
10  - Andy Gross <agross@kernel.org>
11  - Bjorn Andersson <bjorn.andersson@linaro.org>
12  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13
14description:
15  The Shared Memory State Machine facilitates broadcasting of single bit state
16  information between the processors in a Qualcomm SoC. Each processor is
17  assigned 32 bits of state that can be modified. A processor can through a
18  matrix of bitmaps signal subscription of notifications upon changes to a
19  certain bit owned by a certain remote processor.
20
21properties:
22  compatible:
23    const: qcom,smsm
24
25  '#address-cells':
26    const: 1
27
28  qcom,local-host:
29    $ref: /schemas/types.yaml#/definitions/uint32
30    default: 0
31    description:
32      Identifier of the local processor in the list of hosts, or in other words
33      specifier of the column in the subscription matrix representing the local
34      processor.
35
36  '#size-cells':
37    const: 0
38
39patternProperties:
40  "^qcom,ipc-[1-4]$":
41    $ref: /schemas/types.yaml#/definitions/phandle-array
42    items:
43      - items:
44          - description: phandle to a syscon node representing the APCS registers
45          - description: u32 representing offset to the register within the syscon
46          - description: u32 representing the ipc bit within the register
47    description:
48      Three entries specifying the outgoing ipc bit used for signaling the N:th
49      remote processor.
50
51  "@[0-9a-f]$":
52    type: object
53    description:
54      Each processor's state bits are described by a subnode of the SMSM device
55      node.  Nodes can either be flagged as an interrupt-controller to denote a
56      remote processor's state bits or the local processors bits.  The node
57      names are not important.
58
59    properties:
60      reg:
61        maxItems: 1
62
63      interrupt-controller:
64        description:
65          Marks the entry as a interrupt-controller and the state bits to
66          belong to a remote processor.
67
68      '#interrupt-cells':
69        const: 2
70
71      interrupts:
72        maxItems: 1
73        description:
74          One entry specifying remote IRQ used by the remote processor to
75          signal changes of its state bits.
76
77      '#qcom,smem-state-cells':
78        $ref: /schemas/types.yaml#/definitions/uint32
79        const: 1
80        description:
81          Required for local entry. Denotes bit number.
82
83    required:
84      - reg
85
86    oneOf:
87      - required:
88          - '#qcom,smem-state-cells'
89      - required:
90          - interrupt-controller
91          - '#interrupt-cells'
92          - interrupts
93
94    additionalProperties: false
95
96required:
97  - compatible
98  - '#address-cells'
99  - '#size-cells'
100
101anyOf:
102  - required:
103      - qcom,ipc-1
104  - required:
105      - qcom,ipc-2
106  - required:
107      - qcom,ipc-3
108  - required:
109      - qcom,ipc-4
110
111additionalProperties: false
112
113examples:
114  # The following example shows the SMEM setup for controlling properties of
115  # the wireless processor, defined from the 8974 apps processor's
116  # point-of-view. It encompasses one outbound entry and the outgoing interrupt
117  # for the wireless processor.
118  - |
119    #include <dt-bindings/interrupt-controller/arm-gic.h>
120
121    shared-memory {
122        compatible = "qcom,smsm";
123        #address-cells = <1>;
124        #size-cells = <0>;
125        qcom,ipc-3 = <&apcs 8 19>;
126
127        apps_smsm: apps@0 {
128            reg = <0>;
129            #qcom,smem-state-cells = <1>;
130        };
131
132        wcnss_smsm: wcnss@7 {
133            reg = <7>;
134            interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
135            interrupt-controller;
136            #interrupt-cells = <2>;
137        };
138    };
139