xref: /linux/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml (revision 1c07425e902cd3137961c3d45b4271bf8a9b8eb9)
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm RPMH RSC
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Resource Power Manager Hardened (RPMH) is the mechanism for communicating
14  with the hardened resource accelerators on Qualcomm SoCs. Requests to the
15  resources can be written to the Trigger Command Set (TCS)  registers and
16  using a (addr, val) pair and triggered. Messages in the TCS are then sent in
17  sequence over an internal bus.
18
19  The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
20  (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
21  active/wake resource requests. Multiple such DRVs can exist in a SoC and can
22  be written to from Linux. The structure of each DRV follows the same template
23  with a few variations that are captured by the properties here.
24
25  A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
26  have powered off to facilitate idle power saving. TCS could be classified as::
27    ACTIVE  - Triggered by Linux
28    SLEEP   - Triggered by F/W
29    WAKE    - Triggered by F/W
30    CONTROL - Triggered by F/W
31  See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
32
33  The order in which they are described in the DT, should match the hardware
34  configuration.
35
36  Requests can be made for the state of a resource, when the subsystem is
37  active or idle. When all subsystems like Modem, GPU, CPU are idle, the
38  resource state will be an aggregate of the sleep votes from each of those
39  subsystems. Clients may request a sleep value for their shared resources in
40  addition to the active mode requests.
41
42  Drivers that want to use the RSC to communicate with RPMH must specify their
43  bindings as child nodes of the RSC controllers they wish to communicate with.
44
45properties:
46  compatible:
47    const: qcom,rpmh-rsc
48
49  interrupts:
50    minItems: 1
51    maxItems: 4
52    description:
53      The interrupt that trips when a message complete/response is received for
54      this DRV from the accelerators.
55      Number of interrupts must match number of DRV blocks.
56
57  label:
58    description:
59      Name for the RSC. The name would be used in trace logs.
60
61  qcom,drv-id:
62    $ref: /schemas/types.yaml#/definitions/uint32
63    description:
64      The ID of the DRV in the RSC block that will be used by this controller.
65
66  qcom,tcs-config:
67    $ref: /schemas/types.yaml#/definitions/uint32-matrix
68    minItems: 4
69    maxItems: 4
70    items:
71      items:
72        - description: |
73            TCS type::
74             - ACTIVE_TCS
75             - SLEEP_TCS
76             - WAKE_TCS
77             - CONTROL_TCS
78          enum: [ 0, 1, 2, 3 ]
79        - description: Number of TCS
80    description: |
81      The tuple defining the configuration of TCS. Must have two cells which
82      describe each TCS type.  The order of the TCS must match the hardware
83      configuration.
84
85  qcom,tcs-offset:
86    $ref: /schemas/types.yaml#/definitions/uint32
87    description:
88      The offset of the TCS blocks.
89
90  reg:
91    minItems: 1
92    maxItems: 4
93
94  reg-names:
95    minItems: 1
96    items:
97      - const: drv-0
98      - const: drv-1
99      - const: drv-2
100      - const: drv-3
101
102  power-domains:
103    maxItems: 1
104
105  bcm-voter:
106    $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
107
108  clock-controller:
109    $ref: /schemas/clock/qcom,rpmhcc.yaml#
110
111  power-controller:
112    $ref: /schemas/power/qcom,rpmpd.yaml#
113
114patternProperties:
115  '-regulators$':
116    $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
117
118required:
119  - compatible
120  - interrupts
121  - qcom,drv-id
122  - qcom,tcs-config
123  - qcom,tcs-offset
124  - reg
125  - reg-names
126
127additionalProperties: false
128
129examples:
130  - |
131    // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
132    // 2, the register offsets for DRV2 start at 0D00, the register
133    // calculations are like this::
134    // DRV0: 0x179C0000
135    // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
136    // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
137    // TCS-OFFSET: 0xD00
138    #include <dt-bindings/interrupt-controller/arm-gic.h>
139    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
140
141    rsc@179c0000 {
142        compatible = "qcom,rpmh-rsc";
143        reg = <0x179c0000 0x10000>,
144              <0x179d0000 0x10000>,
145              <0x179e0000 0x10000>;
146        reg-names = "drv-0", "drv-1", "drv-2";
147        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
148                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
149                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
150        label = "apps_rsc";
151        qcom,tcs-offset = <0xd00>;
152        qcom,drv-id = <2>;
153        qcom,tcs-config = <ACTIVE_TCS  2>,
154                          <SLEEP_TCS   3>,
155                          <WAKE_TCS    3>,
156                          <CONTROL_TCS 1>;
157        power-domains = <&CLUSTER_PD>;
158      };
159
160  - |
161    // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
162    // register offsets for DRV0 start at 01C00, the register calculations are
163    // like this::
164    // DRV0: 0xAF20000
165    // TCS-OFFSET: 0x1C00
166    #include <dt-bindings/interrupt-controller/arm-gic.h>
167    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
168
169    rsc@af20000 {
170        compatible = "qcom,rpmh-rsc";
171        reg = <0xaf20000 0x10000>;
172        reg-names = "drv-0";
173        interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
174        label = "disp_rsc";
175        qcom,tcs-offset = <0x1c00>;
176        qcom,drv-id = <0>;
177        qcom,tcs-config = <ACTIVE_TCS  0>,
178                          <SLEEP_TCS   1>,
179                          <WAKE_TCS    1>,
180                          <CONTROL_TCS 0>;
181    };
182
183  - |
184    #include <dt-bindings/interrupt-controller/arm-gic.h>
185    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
186    #include <dt-bindings/power/qcom-rpmpd.h>
187
188    rsc@18200000 {
189        compatible = "qcom,rpmh-rsc";
190        reg = <0x18200000 0x10000>,
191              <0x18210000 0x10000>,
192              <0x18220000 0x10000>;
193        reg-names = "drv-0", "drv-1", "drv-2";
194        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
195                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
196                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
197        label = "apps_rsc";
198        qcom,tcs-offset = <0xd00>;
199        qcom,drv-id = <2>;
200        qcom,tcs-config = <ACTIVE_TCS  2>,
201                          <SLEEP_TCS   3>,
202                          <WAKE_TCS    3>,
203                          <CONTROL_TCS 0>;
204        power-domains = <&CLUSTER_PD>;
205
206        clock-controller {
207            compatible = "qcom,sm8350-rpmh-clk";
208            #clock-cells = <1>;
209            clock-names = "xo";
210            clocks = <&xo_board>;
211        };
212
213        power-controller {
214            compatible = "qcom,sm8350-rpmhpd";
215            #power-domain-cells = <1>;
216            operating-points-v2 = <&rpmhpd_opp_table>;
217
218            rpmhpd_opp_table: opp-table {
219                compatible = "operating-points-v2";
220
221                rpmhpd_opp_ret: opp1 {
222                    opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
223                };
224
225                rpmhpd_opp_min_svs: opp2 {
226                    opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
227                };
228
229                rpmhpd_opp_low_svs: opp3 {
230                    opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
231                };
232
233                rpmhpd_opp_svs: opp4 {
234                    opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
235                };
236
237                rpmhpd_opp_svs_l1: opp5 {
238                    opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
239                };
240
241                rpmhpd_opp_nom: opp6 {
242                    opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
243                };
244
245                rpmhpd_opp_nom_l1: opp7 {
246                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
247                };
248
249                rpmhpd_opp_nom_l2: opp8 {
250                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
251                };
252
253                rpmhpd_opp_turbo: opp9 {
254                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
255                };
256
257                rpmhpd_opp_turbo_l1: opp10 {
258                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
259                };
260            };
261        };
262
263        bcm-voter {
264            compatible = "qcom,bcm-voter";
265        };
266    };
267