xref: /linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml (revision a1c3be890440a1769ed6f822376a3e3ab0d42994) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: GENI Serial Engine QUP Wrapper Controller
8
9maintainers:
10  - Mukesh Savaliya <msavaliy@codeaurora.org>
11  - Akash Asthana <akashast@codeaurora.org>
12
13description: |
14 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
15 is a programmable module for supporting a wide range of serial interfaces
16 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
17 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
18 Wrapper controller is modeled as a node with zero or more child nodes each
19 representing a serial engine.
20
21properties:
22  compatible:
23    enum:
24      - qcom,geni-se-qup
25
26  reg:
27    description: QUP wrapper common register address and length.
28    maxItems: 1
29
30  clock-names:
31    items:
32      - const: m-ahb
33      - const: s-ahb
34
35  clocks:
36    items:
37      - description: Master AHB Clock
38      - description: Slave AHB Clock
39
40  "#address-cells":
41    const: 2
42
43  "#size-cells":
44    const: 2
45
46  ranges: true
47
48  interconnects:
49    maxItems: 1
50
51  interconnect-names:
52    const: qup-core
53
54required:
55  - compatible
56  - reg
57  - clock-names
58  - clocks
59  - "#address-cells"
60  - "#size-cells"
61  - ranges
62
63patternProperties:
64  "^.*@[0-9a-f]+$":
65    type: object
66    description: Common properties for GENI Serial Engine based I2C, SPI and
67                 UART controller.
68
69    properties:
70      reg:
71        description: GENI Serial Engine register address and length.
72        maxItems: 1
73
74      clock-names:
75        const: se
76
77      clocks:
78        description: Serial engine core clock needed by the device.
79        maxItems: 1
80
81      interconnects:
82        minItems: 2
83        maxItems: 3
84
85      interconnect-names:
86        minItems: 2
87        items:
88          - const: qup-core
89          - const: qup-config
90          - const: qup-memory
91
92    required:
93      - reg
94      - clock-names
95      - clocks
96
97  "spi@[0-9a-f]+$":
98    type: object
99    description: GENI serial engine based SPI controller. SPI in master mode
100                 supports up to 50MHz, up to four chip selects, programmable
101                 data path from 4 bits to 32 bits and numerous protocol
102                 variants.
103    $ref: /spi/spi-controller.yaml#
104
105    properties:
106      compatible:
107        enum:
108          - qcom,geni-spi
109
110      interrupts:
111        maxItems: 1
112
113      "#address-cells":
114        const: 1
115
116      "#size-cells":
117        const: 0
118
119    required:
120      - compatible
121      - interrupts
122      - "#address-cells"
123      - "#size-cells"
124
125  "i2c@[0-9a-f]+$":
126    type: object
127    description: GENI serial engine based I2C controller.
128    $ref: /schemas/i2c/i2c-controller.yaml#
129
130    properties:
131      compatible:
132        enum:
133          - qcom,geni-i2c
134
135      interrupts:
136        maxItems: 1
137
138      "#address-cells":
139        const: 1
140
141      "#size-cells":
142        const: 0
143
144      clock-frequency:
145        description: Desired I2C bus clock frequency in Hz.
146        default: 100000
147
148    required:
149      - compatible
150      - interrupts
151      - "#address-cells"
152      - "#size-cells"
153
154  "serial@[0-9a-f]+$":
155    type: object
156    description: GENI Serial Engine based UART Controller.
157    $ref: /schemas/serial.yaml#
158
159    properties:
160      compatible:
161        enum:
162          - qcom,geni-uart
163          - qcom,geni-debug-uart
164
165      interrupts:
166        minItems: 1
167        maxItems: 2
168        items:
169          - description: UART core irq
170          - description: Wakeup irq (RX GPIO)
171
172    required:
173      - compatible
174      - interrupts
175
176additionalProperties: false
177
178examples:
179  - |
180    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
181    #include <dt-bindings/interrupt-controller/arm-gic.h>
182
183    soc {
184        #address-cells = <2>;
185        #size-cells = <2>;
186
187        geniqup@8c0000 {
188            compatible = "qcom,geni-se-qup";
189            reg = <0 0x008c0000 0 0x6000>;
190            clock-names = "m-ahb", "s-ahb";
191            clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
192                <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
193            #address-cells = <2>;
194            #size-cells = <2>;
195            ranges;
196
197            i2c0: i2c@a94000 {
198                compatible = "qcom,geni-i2c";
199                reg = <0 0xa94000 0 0x4000>;
200                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
201                clock-names = "se";
202                clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
203                pinctrl-names = "default", "sleep";
204                pinctrl-0 = <&qup_1_i2c_5_active>;
205                pinctrl-1 = <&qup_1_i2c_5_sleep>;
206                #address-cells = <1>;
207                #size-cells = <0>;
208            };
209
210            uart0: serial@a88000 {
211                compatible = "qcom,geni-uart";
212                reg = <0 0xa88000 0 0x7000>;
213                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
214                clock-names = "se";
215                clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
216                pinctrl-names = "default", "sleep";
217                pinctrl-0 = <&qup_1_uart_3_active>;
218                pinctrl-1 = <&qup_1_uart_3_sleep>;
219            };
220        };
221    };
222
223...
224