xref: /linux/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml (revision fc2d791a43d3880496d1c729b8bd74d2c19cb4e7) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region
8
9maintainers:
10  - Conor Dooley <conor.dooley@microchip.com>
11
12description:
13  An wide assortment of registers that control elements of the MSS on PolarFire
14  SoC, including pinmuxing, resets and clocks among others.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - const: microchip,mpfs-mss-top-sysreg
21          - const: syscon
22          - const: simple-mfd
23      - items:
24          - const: microchip,pic64gx-mss-top-sysreg
25          - const: microchip,mpfs-mss-top-sysreg
26          - const: syscon
27          - const: simple-mfd
28
29  reg:
30    maxItems: 1
31
32  '#address-cells':
33    const: 1
34
35  '#size-cells':
36    const: 1
37
38  '#reset-cells':
39    description:
40      The AHB/AXI peripherals on the PolarFire SoC have reset support, so
41      from CLK_ENVM to CLK_CFM. The reset consumer should specify the
42      desired peripheral via the clock ID in its "resets" phandle cell.
43      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list
44      of PolarFire clock/reset IDs.
45    const: 1
46
47  interrupt-controller@54:
48    type: object
49    $ref: /schemas/soc/microchip/microchip,mpfs-irqmux.yaml
50
51  pinctrl@200:
52    type: object
53    $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
54
55  pinctrl@204:
56    type: object
57    $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml
58
59required:
60  - compatible
61  - reg
62
63additionalProperties: false
64
65examples:
66  - |
67    syscon@20002000 {
68      compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
69      reg = <0x20002000 0x1000>;
70      #reset-cells = <1>;
71    };
72
73