xref: /linux/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml (revision a110f942672c8995dc1cacb5a44c6730856743aa) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region
8
9maintainers:
10  - Conor Dooley <conor.dooley@microchip.com>
11
12description:
13  An wide assortment of registers that control elements of the MSS on PolarFire
14  SoC, including pinmuxing, resets and clocks among others.
15
16properties:
17  compatible:
18    items:
19      - const: microchip,mpfs-mss-top-sysreg
20      - const: syscon
21      - const: simple-mfd
22
23  reg:
24    maxItems: 1
25
26  '#address-cells':
27    const: 1
28
29  '#size-cells':
30    const: 1
31
32  '#reset-cells':
33    description:
34      The AHB/AXI peripherals on the PolarFire SoC have reset support, so
35      from CLK_ENVM to CLK_CFM. The reset consumer should specify the
36      desired peripheral via the clock ID in its "resets" phandle cell.
37      See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list
38      of PolarFire clock/reset IDs.
39    const: 1
40
41  pinctrl@200:
42    type: object
43    $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
44
45required:
46  - compatible
47  - reg
48
49additionalProperties: false
50
51examples:
52  - |
53    syscon@20002000 {
54      compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
55      reg = <0x20002000 0x1000>;
56      #reset-cells = <1>;
57    };
58
59