1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Atmel Timer Counter Block 8 9maintainers: 10 - Alexandre Belloni <alexandre.belloni@bootlin.com> 11 12description: | 13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each 14 timer has three channels with two counters each. 15 16properties: 17 compatible: 18 oneOf: 19 - items: 20 - enum: 21 - atmel,at91rm9200-tcb 22 - atmel,at91sam9x5-tcb 23 - atmel,sama5d2-tcb 24 - const: simple-mfd 25 - const: syscon 26 - items: 27 - const: microchip,sam9x7-tcb 28 - const: atmel,sama5d2-tcb 29 - const: simple-mfd 30 - const: syscon 31 32 reg: 33 maxItems: 1 34 35 interrupts: 36 description: 37 List of interrupts. One interrupt per TCB channel if available or one 38 interrupt for the TC block 39 minItems: 1 40 maxItems: 3 41 42 clock-names: 43 description: 44 List of clock names. Always includes t0_clk and slow clk. Also includes 45 t1_clk and t2_clk if a clock per channel is available. 46 minItems: 2 47 maxItems: 4 48 49 clocks: 50 minItems: 2 51 maxItems: 4 52 53 '#address-cells': 54 const: 1 55 56 '#size-cells': 57 const: 0 58 59patternProperties: 60 "^timer@[0-2]$": 61 description: The timer block channels that are used as timers or counters. 62 type: object 63 additionalProperties: false 64 properties: 65 compatible: 66 items: 67 - enum: 68 - atmel,tcb-timer 69 - atmel,tcb-pwm 70 - microchip,tcb-capture 71 reg: 72 description: 73 List of channels to use for this particular timer. In Microchip TCB capture 74 mode channels are registered as a counter devices, for the qdec mode TCB0's 75 channel <0> and <1> are required. 76 77 minItems: 1 78 maxItems: 3 79 required: 80 - compatible 81 - reg 82 83 "^pwm@[0-2]$": 84 description: The timer block channels that are used as PWMs. 85 $ref: /schemas/pwm/pwm.yaml# 86 type: object 87 properties: 88 compatible: 89 const: atmel,tcb-pwm 90 reg: 91 description: 92 TCB channel to use for this PWM. 93 enum: [ 0, 1, 2 ] 94 95 "#pwm-cells": 96 description: 97 The only third cell flag supported by this binding is 98 PWM_POLARITY_INVERTED. 99 const: 3 100 101 required: 102 - compatible 103 - reg 104 - "#pwm-cells" 105 106 additionalProperties: false 107 108 109allOf: 110 - if: 111 properties: 112 compatible: 113 contains: 114 const: atmel,sama5d2-tcb 115 then: 116 properties: 117 clocks: 118 minItems: 3 119 maxItems: 3 120 clock-names: 121 items: 122 - const: t0_clk 123 - const: gclk 124 - const: slow_clk 125 else: 126 properties: 127 clocks: 128 minItems: 2 129 maxItems: 4 130 clock-names: 131 oneOf: 132 - items: 133 - const: t0_clk 134 - const: slow_clk 135 - items: 136 - const: t0_clk 137 - const: t1_clk 138 - const: t2_clk 139 - const: slow_clk 140 141required: 142 - compatible 143 - reg 144 - interrupts 145 - clocks 146 - clock-names 147 - '#address-cells' 148 - '#size-cells' 149 150additionalProperties: false 151 152examples: 153 - | 154 /* One interrupt per TC block: */ 155 tcb0: timer@fff7c000 { 156 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 reg = <0xfff7c000 0x100>; 160 interrupts = <18 4>; 161 clocks = <&tcb0_clk>, <&clk32k>; 162 clock-names = "t0_clk", "slow_clk"; 163 164 timer@0 { 165 compatible = "atmel,tcb-timer"; 166 reg = <0>, <1>; 167 }; 168 169 timer@2 { 170 compatible = "atmel,tcb-timer"; 171 reg = <2>; 172 }; 173 }; 174 175 /* One interrupt per TC channel in a TC block: */ 176 tcb1: timer@fffdc000 { 177 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 reg = <0xfffdc000 0x100>; 181 interrupts = <26 4>, <27 4>, <28 4>; 182 clocks = <&tcb1_clk>, <&clk32k>; 183 clock-names = "t0_clk", "slow_clk"; 184 185 timer@0 { 186 compatible = "atmel,tcb-timer"; 187 reg = <0>; 188 }; 189 190 timer@1 { 191 compatible = "atmel,tcb-timer"; 192 reg = <1>; 193 }; 194 195 pwm@2 { 196 compatible = "atmel,tcb-pwm"; 197 reg = <2>; 198 #pwm-cells = <3>; 199 }; 200 }; 201 /* TCB0 Capture with QDEC: */ 202 timer@f800c000 { 203 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 reg = <0xfff7c000 0x100>; 207 interrupts = <18 4>; 208 clocks = <&tcb0_clk>, <&clk32k>; 209 clock-names = "t0_clk", "slow_clk"; 210 211 timer@0 { 212 compatible = "microchip,tcb-capture"; 213 reg = <0>, <1>; 214 }; 215 216 timer@2 { 217 compatible = "atmel,tcb-timer"; 218 reg = <2>; 219 }; 220 }; 221