xref: /linux/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml (revision 6f84981772535e670e4e2df051a672af229b6694) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Smart Voltage Scaling (SVS)
8
9maintainers:
10  - Roger Lu <roger.lu@mediatek.com>
11  - Matthias Brugger <matthias.bgg@gmail.com>
12  - Kevin Hilman <khilman@kernel.org>
13
14description: |+
15  The SVS engine is a piece of hardware which has several
16  controllers(banks) for calculating suitable voltage to
17  different power domains(CPU/GPU/CCI) according to
18  chip process corner, temperatures and other factors. Then DVFS
19  driver could apply SVS bank voltage to PMIC/Buck.
20
21properties:
22  compatible:
23    enum:
24      - mediatek,mt8183-svs
25      - mediatek,mt8192-svs
26
27  reg:
28    maxItems: 1
29    description: Address range of the MTK SVS controller.
30
31  interrupts:
32    maxItems: 1
33
34  clocks:
35    maxItems: 1
36    description: Main clock for MTK SVS controller to work.
37
38  clock-names:
39    const: main
40
41  nvmem-cells:
42    minItems: 1
43    description:
44      Phandle to the calibration data provided by a nvmem device.
45    items:
46      - description: SVS efuse for SVS controller
47      - description: Thermal efuse for SVS controller
48
49  nvmem-cell-names:
50    items:
51      - const: svs-calibration-data
52      - const: t-calibration-data
53
54  resets:
55    maxItems: 1
56
57  reset-names:
58    items:
59      - const: svs_rst
60
61required:
62  - compatible
63  - reg
64  - interrupts
65  - clocks
66  - clock-names
67  - nvmem-cells
68  - nvmem-cell-names
69
70additionalProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/mt8183-clk.h>
75    #include <dt-bindings/interrupt-controller/arm-gic.h>
76    #include <dt-bindings/interrupt-controller/irq.h>
77
78    soc {
79        #address-cells = <2>;
80        #size-cells = <2>;
81
82        svs@1100b000 {
83            compatible = "mediatek,mt8183-svs";
84            reg = <0 0x1100b000 0 0x1000>;
85            interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
86            clocks = <&infracfg CLK_INFRA_THERM>;
87            clock-names = "main";
88            nvmem-cells = <&svs_calibration>, <&thermal_calibration>;
89            nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
90        };
91    };
92