xref: /linux/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Write Direct Memory Access
8
9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11  - Moudy Ho <moudy.ho@mediatek.com>
12
13description: |
14  MediaTek Write Direct Memory Access(WDMA) component used to write
15  the data into DMA.
16
17properties:
18  compatible:
19    items:
20      - enum:
21          - mediatek,mt8183-mdp3-wdma
22
23  reg:
24    maxItems: 1
25
26  mediatek,gce-client-reg:
27    $ref: /schemas/types.yaml#/definitions/phandle-array
28    items:
29      items:
30        - description: phandle of GCE
31        - description: GCE subsys id
32        - description: register offset
33        - description: register size
34    description: The register of client driver can be configured by gce with
35      4 arguments defined in this property. Each GCE subsys id is mapping to
36      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
37
38  mediatek,gce-events:
39    description:
40      The event id which is mapping to the specific hardware event signal
41      to gce. The event id is defined in the gce header
42      include/dt-bindings/gce/<chip>-gce.h of each chips.
43    $ref: /schemas/types.yaml#/definitions/uint32-array
44
45  power-domains:
46    maxItems: 1
47
48  clocks:
49    minItems: 1
50
51  iommus:
52    maxItems: 1
53
54required:
55  - compatible
56  - reg
57  - mediatek,gce-client-reg
58  - mediatek,gce-events
59  - power-domains
60  - clocks
61  - iommus
62
63additionalProperties: false
64
65examples:
66  - |
67    #include <dt-bindings/clock/mt8183-clk.h>
68    #include <dt-bindings/gce/mt8183-gce.h>
69    #include <dt-bindings/power/mt8183-power.h>
70    #include <dt-bindings/memory/mt8183-larb-port.h>
71
72    mdp3_wdma: mdp3-wdma@14006000 {
73      compatible = "mediatek,mt8183-mdp3-wdma";
74      reg = <0x14006000 0x1000>;
75      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
76      mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
77                            <CMDQ_EVENT_MDP_WDMA0_EOF>;
78      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
79      clocks = <&mmsys CLK_MM_MDP_WDMA0>;
80      iommus = <&iommu>;
81    };
82