xref: /linux/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml (revision 55d0969c451159cff86949b38c39171cab962069) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek mutex
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
15  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
16  data path or MDP data path.
17  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
18  the shadow register.
19  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
20  For a description of the MMSYS_CONFIG binding, see
21  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
22  for details.
23
24properties:
25  compatible:
26    enum:
27      - mediatek,mt2701-disp-mutex
28      - mediatek,mt2712-disp-mutex
29      - mediatek,mt6795-disp-mutex
30      - mediatek,mt8167-disp-mutex
31      - mediatek,mt8173-disp-mutex
32      - mediatek,mt8183-disp-mutex
33      - mediatek,mt8186-disp-mutex
34      - mediatek,mt8186-mdp3-mutex
35      - mediatek,mt8188-disp-mutex
36      - mediatek,mt8188-vpp-mutex
37      - mediatek,mt8192-disp-mutex
38      - mediatek,mt8195-disp-mutex
39      - mediatek,mt8195-vpp-mutex
40      - mediatek,mt8365-disp-mutex
41
42  reg:
43    maxItems: 1
44
45  interrupts:
46    maxItems: 1
47
48  power-domains:
49    description: A phandle and PM domain specifier as defined by bindings of
50      the power controller specified by phandle. See
51      Documentation/devicetree/bindings/power/power-domain.yaml for details.
52
53  clocks:
54    items:
55      - description: MUTEX Clock
56
57  mediatek,gce-events:
58    description:
59      The event id which is mapping to the specific hardware event signal
60      to gce. The event id is defined in the gce header
61      include/dt-bindings/gce/<chip>-gce.h of each chips.
62    $ref: /schemas/types.yaml#/definitions/uint32-array
63
64  mediatek,gce-client-reg:
65    $ref: /schemas/types.yaml#/definitions/phandle-array
66    items:
67      items:
68        - description: phandle of GCE
69        - description: GCE subsys id
70        - description: register offset
71        - description: register size
72    description: The register of client driver can be configured by gce with
73      4 arguments defined in this property. Each GCE subsys id is mapping to
74      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
75
76allOf:
77  - if:
78      properties:
79        compatible:
80          contains:
81            enum:
82              - mediatek,mt2701-disp-mutex
83              - mediatek,mt2712-disp-mutex
84              - mediatek,mt6795-disp-mutex
85              - mediatek,mt8173-disp-mutex
86              - mediatek,mt8186-disp-mutex
87              - mediatek,mt8186-mdp3-mutex
88              - mediatek,mt8192-disp-mutex
89              - mediatek,mt8195-disp-mutex
90    then:
91      required:
92        - clocks
93
94
95required:
96  - compatible
97  - reg
98  - interrupts
99  - power-domains
100
101additionalProperties: false
102
103examples:
104  - |
105    #include <dt-bindings/interrupt-controller/arm-gic.h>
106    #include <dt-bindings/clock/mt8173-clk.h>
107    #include <dt-bindings/power/mt8173-power.h>
108    #include <dt-bindings/gce/mt8173-gce.h>
109
110    soc {
111        #address-cells = <2>;
112        #size-cells = <2>;
113
114        mutex: mutex@14020000 {
115            compatible = "mediatek,mt8173-disp-mutex";
116            reg = <0 0x14020000 0 0x1000>;
117            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
118            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
119            clocks = <&mmsys CLK_MM_MUTEX_32K>;
120            mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
121                                  <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
122        };
123    };
124