xref: /linux/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml (revision 4359a011e259a4608afc7fb3635370c9d4ba5943) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek mutex
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
15  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
16  data path or MDP data path.
17  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
18  the shadow register.
19  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
20  For a description of the MMSYS_CONFIG binding, see
21  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
22  for details.
23
24properties:
25  compatible:
26    enum:
27      - mediatek,mt2701-disp-mutex
28      - mediatek,mt2712-disp-mutex
29      - mediatek,mt8167-disp-mutex
30      - mediatek,mt8173-disp-mutex
31      - mediatek,mt8183-disp-mutex
32      - mediatek,mt8186-disp-mutex
33      - mediatek,mt8192-disp-mutex
34      - mediatek,mt8195-disp-mutex
35
36  reg:
37    maxItems: 1
38
39  interrupts:
40    maxItems: 1
41
42  power-domains:
43    description: A phandle and PM domain specifier as defined by bindings of
44      the power controller specified by phandle. See
45      Documentation/devicetree/bindings/power/power-domain.yaml for details.
46
47  clocks:
48    items:
49      - description: MUTEX Clock
50
51  mediatek,gce-events:
52    description:
53      The event id which is mapping to the specific hardware event signal
54      to gce. The event id is defined in the gce header
55      include/dt-bindings/gce/<chip>-gce.h of each chips.
56    $ref: /schemas/types.yaml#/definitions/uint32-array
57
58  mediatek,gce-client-reg:
59    $ref: /schemas/types.yaml#/definitions/phandle-array
60    items:
61      items:
62        - description: phandle of GCE
63        - description: GCE subsys id
64        - description: register offset
65        - description: register size
66    description: The register of client driver can be configured by gce with
67      4 arguments defined in this property. Each GCE subsys id is mapping to
68      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
69
70required:
71  - compatible
72  - reg
73  - interrupts
74  - power-domains
75  - clocks
76
77additionalProperties: false
78
79examples:
80  - |
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82    #include <dt-bindings/clock/mt8173-clk.h>
83    #include <dt-bindings/power/mt8173-power.h>
84    #include <dt-bindings/gce/mt8173-gce.h>
85
86    soc {
87        #address-cells = <2>;
88        #size-cells = <2>;
89
90        mutex: mutex@14020000 {
91            compatible = "mediatek,mt8173-disp-mutex";
92            reg = <0 0x14020000 0 0x1000>;
93            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
94            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
95            clocks = <&mmsys CLK_MM_MUTEX_32K>;
96            mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
97                                  <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
98        };
99    };
100