xref: /linux/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml (revision 3a2c4d55e32ad65efebdb6de44eef3bfa08bb49d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Mute-X
8
9maintainers:
10  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12  - Philipp Zabel <p.zabel@pengutronix.de>
13
14description:
15  MediaTek Mute-X, namely MUTEX, is used to "mute" or "unmute" trigger signals
16  like Start Of Frame (SOF), End Of Frame (EOF), Tearing Effect (TE / VSYNC)
17  and others to each hardware sub-modules in the Display Controller IP or in
18  the Media Data Path (MDP) IP.
19  In some SoCs like MT2701, this hardware module may feature functionality
20  to, for example, protect shadow registers by blocking auto write triggers
21  upon operation (usually frame push) completion.
22  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
23  For a description of the MMSYS_CONFIG binding, see
24  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
25  for details.
26
27properties:
28  compatible:
29    enum:
30      - mediatek,mt2701-disp-mutex
31      - mediatek,mt2712-disp-mutex
32      - mediatek,mt6795-disp-mutex
33      - mediatek,mt8167-disp-mutex
34      - mediatek,mt8173-disp-mutex
35      - mediatek,mt8183-disp-mutex
36      - mediatek,mt8186-disp-mutex
37      - mediatek,mt8186-mdp3-mutex
38      - mediatek,mt8188-disp-mutex
39      - mediatek,mt8188-vpp-mutex
40      - mediatek,mt8192-disp-mutex
41      - mediatek,mt8195-disp-mutex
42      - mediatek,mt8195-vpp-mutex
43      - mediatek,mt8365-disp-mutex
44
45  reg:
46    maxItems: 1
47
48  interrupts:
49    maxItems: 1
50
51  power-domains:
52    description: A phandle and PM domain specifier as defined by bindings of
53      the power controller specified by phandle. See
54      Documentation/devicetree/bindings/power/power-domain.yaml for details.
55
56  clocks:
57    items:
58      - description: MUTEX Clock
59
60  mediatek,gce-events:
61    description:
62      The event id which is mapping to the specific hardware event signal
63      to gce. The event id is defined in the gce header
64      include/dt-bindings/gce/<chip>-gce.h of each chips.
65    $ref: /schemas/types.yaml#/definitions/uint32-array
66
67  mediatek,gce-client-reg:
68    $ref: /schemas/types.yaml#/definitions/phandle-array
69    items:
70      items:
71        - description: phandle of GCE
72        - description: GCE subsys id
73        - description: register offset
74        - description: register size
75    description: The register of client driver can be configured by gce with
76      4 arguments defined in this property. Each GCE subsys id is mapping to
77      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
78
79allOf:
80  - if:
81      properties:
82        compatible:
83          contains:
84            enum:
85              - mediatek,mt2701-disp-mutex
86              - mediatek,mt2712-disp-mutex
87              - mediatek,mt6795-disp-mutex
88              - mediatek,mt8173-disp-mutex
89              - mediatek,mt8186-disp-mutex
90              - mediatek,mt8186-mdp3-mutex
91              - mediatek,mt8192-disp-mutex
92              - mediatek,mt8195-disp-mutex
93    then:
94      required:
95        - clocks
96
97required:
98  - compatible
99  - reg
100  - interrupts
101  - power-domains
102
103additionalProperties: false
104
105examples:
106  - |
107    #include <dt-bindings/interrupt-controller/arm-gic.h>
108    #include <dt-bindings/clock/mt8173-clk.h>
109    #include <dt-bindings/power/mt8173-power.h>
110    #include <dt-bindings/gce/mt8173-gce.h>
111
112    soc {
113        #address-cells = <2>;
114        #size-cells = <2>;
115
116        mutex: mutex@14020000 {
117            compatible = "mediatek,mt8173-disp-mutex";
118            reg = <0 0x14020000 0 0x1000>;
119            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
120            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
121            clocks = <&mmsys CLK_MM_MUTEX_32K>;
122            mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
123                                  <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
124        };
125    };
126