xref: /linux/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml (revision 9320fad102b0d14a007fa6d4293d00eede6e730a)
1182c4e1fSLucas Stach# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2182c4e1fSLucas Stach%YAML 1.2
3182c4e1fSLucas Stach---
4182c4e1fSLucas Stach$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml#
5182c4e1fSLucas Stach$schema: http://devicetree.org/meta-schemas/core.yaml#
6182c4e1fSLucas Stach
7182c4e1fSLucas Stachtitle: NXP i.MX8MQ VPU blk-ctrl
8182c4e1fSLucas Stach
9182c4e1fSLucas Stachmaintainers:
10182c4e1fSLucas Stach  - Lucas Stach <l.stach@pengutronix.de>
11182c4e1fSLucas Stach
12182c4e1fSLucas Stachdescription:
13182c4e1fSLucas Stach  The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to
14182c4e1fSLucas Stach  the NoC and ensuring proper power sequencing of the VPU peripherals
15182c4e1fSLucas Stach  located in the VPU domain of the SoC.
16182c4e1fSLucas Stach
17182c4e1fSLucas Stachproperties:
18182c4e1fSLucas Stach  compatible:
19182c4e1fSLucas Stach    items:
20182c4e1fSLucas Stach      - const: fsl,imx8mq-vpu-blk-ctrl
21182c4e1fSLucas Stach
22182c4e1fSLucas Stach  reg:
23182c4e1fSLucas Stach    maxItems: 1
24182c4e1fSLucas Stach
25182c4e1fSLucas Stach  '#power-domain-cells':
26182c4e1fSLucas Stach    const: 1
27182c4e1fSLucas Stach
28182c4e1fSLucas Stach  power-domains:
29182c4e1fSLucas Stach    minItems: 3
30182c4e1fSLucas Stach    maxItems: 3
31182c4e1fSLucas Stach
32182c4e1fSLucas Stach  power-domain-names:
33182c4e1fSLucas Stach    items:
34182c4e1fSLucas Stach      - const: bus
35182c4e1fSLucas Stach      - const: g1
36182c4e1fSLucas Stach      - const: g2
37182c4e1fSLucas Stach
38182c4e1fSLucas Stach  clocks:
39182c4e1fSLucas Stach    minItems: 2
40182c4e1fSLucas Stach    maxItems: 2
41182c4e1fSLucas Stach
42182c4e1fSLucas Stach  clock-names:
43182c4e1fSLucas Stach    items:
44182c4e1fSLucas Stach      - const: g1
45182c4e1fSLucas Stach      - const: g2
46182c4e1fSLucas Stach
47182c4e1fSLucas Stachrequired:
48182c4e1fSLucas Stach  - compatible
49182c4e1fSLucas Stach  - reg
50182c4e1fSLucas Stach  - power-domains
51182c4e1fSLucas Stach  - power-domain-names
52182c4e1fSLucas Stach  - clocks
53182c4e1fSLucas Stach  - clock-names
54182c4e1fSLucas Stach
55182c4e1fSLucas StachadditionalProperties: false
56182c4e1fSLucas Stach
57182c4e1fSLucas Stachexamples:
58182c4e1fSLucas Stach  - |
59182c4e1fSLucas Stach    #include <dt-bindings/clock/imx8mq-clock.h>
60182c4e1fSLucas Stach    #include <dt-bindings/power/imx8mq-power.h>
61182c4e1fSLucas Stach
62*9320fad1SMarek Vasut    blk-ctrl@38320000 {
63182c4e1fSLucas Stach      compatible = "fsl,imx8mq-vpu-blk-ctrl";
64182c4e1fSLucas Stach      reg = <0x38320000 0x100>;
65182c4e1fSLucas Stach      power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
66182c4e1fSLucas Stach      power-domain-names = "bus", "g1", "g2";
67182c4e1fSLucas Stach      clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
68182c4e1fSLucas Stach               <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
69182c4e1fSLucas Stach      clock-names = "g1", "g2";
70182c4e1fSLucas Stach      #power-domain-cells = <1>;
71182c4e1fSLucas Stach    };
72