xref: /linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml (revision a6021aa24f6417416d93318bbfa022ab229c33c8) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PowerQUICC QE QUICC Multichannel Controller (QMC)
8
9maintainers:
10  - Herve Codina <herve.codina@bootlin.com>
11
12description:
13  The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one
14  serial controller using the same TDM physical interface routed from TSA.
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - fsl,mpc8321-ucc-qmc
21      - const: fsl,qe-ucc-qmc
22
23  reg:
24    items:
25      - description: UCC (Unified communication controller) register base
26      - description: Dual port ram base
27
28  reg-names:
29    items:
30      - const: ucc_regs
31      - const: dpram
32
33  interrupts:
34    maxItems: 1
35    description: UCC interrupt line in the QE interrupt controller
36
37  fsl,tsa-serial:
38    $ref: /schemas/types.yaml#/definitions/phandle-array
39    items:
40      - items:
41          - description: phandle to TSA node
42          - enum: [1, 2, 3, 4, 5]
43            description: |
44              TSA serial interface (dt-bindings/soc/qe-fsl,tsa.h defines these
45              values)
46               - 1: UCC1
47               - 2: UCC2
48               - 3: UCC3
49               - 4: UCC4
50               - 5: UCC5
51    description:
52      Should be a phandle/number pair. The phandle to TSA node and the TSA
53      serial interface to use.
54
55  fsl,soft-qmc:
56    $ref: /schemas/types.yaml#/definitions/string
57    description:
58      Soft QMC firmware name to load. If this property is omitted, no firmware
59      are used.
60
61  '#address-cells':
62    const: 1
63
64  '#size-cells':
65    const: 0
66
67patternProperties:
68  '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
69    description:
70      A channel managed by this controller
71    type: object
72    additionalProperties: false
73
74    properties:
75      compatible:
76        items:
77          - enum:
78              - fsl,mpc8321-ucc-qmc-hdlc
79          - const: fsl,qe-ucc-qmc-hdlc
80          - const: fsl,qmc-hdlc
81
82      reg:
83        minimum: 0
84        maximum: 63
85        description:
86          The channel number
87
88      fsl,operational-mode:
89        $ref: /schemas/types.yaml#/definitions/string
90        enum: [transparent, hdlc]
91        default: transparent
92        description: |
93          The channel operational mode
94            - hdlc: The channel handles HDLC frames
95            - transparent: The channel handles raw data without any processing
96
97      fsl,reverse-data:
98        $ref: /schemas/types.yaml#/definitions/flag
99        description:
100          The bit order as seen on the channels is reversed,
101          transmitting/receiving the MSB of each octet first.
102          This flag is used only in 'transparent' mode.
103
104      fsl,tx-ts-mask:
105        $ref: /schemas/types.yaml#/definitions/uint64
106        description:
107          Channel assigned Tx time-slots within the Tx time-slots routed by the
108          TSA to this cell.
109
110      fsl,rx-ts-mask:
111        $ref: /schemas/types.yaml#/definitions/uint64
112        description:
113          Channel assigned Rx time-slots within the Rx time-slots routed by the
114          TSA to this cell.
115
116      fsl,framer:
117        $ref: /schemas/types.yaml#/definitions/phandle
118        description:
119          phandle to the framer node. The framer is in charge of an E1/T1 line
120          interface connected to the TDM bus. It can be used to get the E1/T1 line
121          status such as link up/down.
122
123    allOf:
124      - if:
125          properties:
126            compatible:
127              not:
128                contains:
129                  const: fsl,qmc-hdlc
130        then:
131          properties:
132            fsl,framer: false
133
134    required:
135      - reg
136      - fsl,tx-ts-mask
137      - fsl,rx-ts-mask
138
139required:
140  - compatible
141  - reg
142  - reg-names
143  - interrupts
144  - fsl,tsa-serial
145  - '#address-cells'
146  - '#size-cells'
147
148additionalProperties: false
149
150examples:
151  - |
152    #include <dt-bindings/soc/qe-fsl,tsa.h>
153
154    qmc@a60 {
155        compatible = "fsl,mpc8321-ucc-qmc", "fsl,qe-ucc-qmc";
156        reg = <0x3200 0x200>,
157              <0x10000 0x1000>;
158        reg-names = "ucc_regs", "dpram";
159        interrupts = <35>;
160        interrupt-parent = <&qeic>;
161        fsl,soft-qmc = "fsl_qe_ucode_qmc_8321_11.bin";
162
163        #address-cells = <1>;
164        #size-cells = <0>;
165
166        fsl,tsa-serial = <&tsa FSL_QE_TSA_UCC4>;
167
168        channel@16 {
169            /* Ch16 : First 4 even TS from all routed from TSA */
170            reg = <16>;
171            fsl,operational-mode = "transparent";
172            fsl,reverse-data;
173            fsl,tx-ts-mask = <0x00000000 0x000000aa>;
174            fsl,rx-ts-mask = <0x00000000 0x000000aa>;
175        };
176
177        channel@17 {
178            /* Ch17 : First 4 odd TS from all routed from TSA */
179            reg = <17>;
180            fsl,operational-mode = "transparent";
181            fsl,reverse-data;
182            fsl,tx-ts-mask = <0x00000000 0x00000055>;
183            fsl,rx-ts-mask = <0x00000000 0x00000055>;
184        };
185
186        channel@19 {
187            /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
188            compatible = "fsl,mpc8321-ucc-qmc-hdlc",
189                         "fsl,qe-ucc-qmc-hdlc",
190                         "fsl,qmc-hdlc";
191            reg = <19>;
192            fsl,operational-mode = "hdlc";
193            fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
194            fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
195            fsl,framer = <&framer>;
196        };
197    };
198