1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: PowerQUICC QE Time-slot assigner (TSA) controller 8 9maintainers: 10 - Herve Codina <herve.codina@bootlin.com> 11 12description: 13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. 14 Its purpose is to route some TDM time-slots to other internal serial 15 controllers. 16 17properties: 18 compatible: 19 items: 20 - enum: 21 - fsl,mpc8321-tsa 22 - const: fsl,qe-tsa 23 24 reg: 25 items: 26 - description: SI (Serial Interface) register base 27 - description: SI RAM base 28 29 reg-names: 30 items: 31 - const: si_regs 32 - const: si_ram 33 34 '#address-cells': 35 const: 1 36 37 '#size-cells': 38 const: 0 39 40patternProperties: 41 '^tdm@[0-3]$': 42 description: 43 The TDM managed by this controller 44 type: object 45 46 additionalProperties: false 47 48 properties: 49 reg: 50 minimum: 0 51 maximum: 3 52 description: 53 The TDM number for this TDM, 0 for TDMa, 1 for TDMb, 2 for TDMc and 3 54 for TDMd. 55 56 fsl,common-rxtx-pins: 57 $ref: /schemas/types.yaml#/definitions/flag 58 description: 59 The hardware can use four dedicated pins for Tx clock, Tx sync, Rx 60 clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync. 61 Without the 'fsl,common-rxtx-pins' property, the four pins are used. 62 With the 'fsl,common-rxtx-pins' property, two pins are used. 63 64 clocks: 65 minItems: 2 66 items: 67 - description: Receive sync clock 68 - description: Receive data clock 69 - description: Transmit sync clock 70 - description: Transmit data clock 71 72 clock-names: 73 minItems: 2 74 items: 75 - const: rsync 76 - const: rclk 77 - const: tsync 78 - const: tclk 79 80 fsl,rx-frame-sync-delay-bits: 81 enum: [0, 1, 2, 3] 82 default: 0 83 description: | 84 Receive frame sync delay in number of bits. 85 Indicates the delay between the Rx sync and the first bit of the Rx 86 frame. 87 88 fsl,tx-frame-sync-delay-bits: 89 enum: [0, 1, 2, 3] 90 default: 0 91 description: | 92 Transmit frame sync delay in number of bits. 93 Indicates the delay between the Tx sync and the first bit of the Tx 94 frame. 95 96 fsl,clock-falling-edge: 97 $ref: /schemas/types.yaml#/definitions/flag 98 description: 99 Data is sent on falling edge of the clock (and received on the rising 100 edge). If not present, data is sent on the rising edge (and received 101 on the falling edge). 102 103 fsl,fsync-rising-edge: 104 $ref: /schemas/types.yaml#/definitions/flag 105 description: 106 Frame sync pulses are sampled with the rising edge of the channel 107 clock. If not present, pulses are sampled with the falling edge. 108 109 fsl,fsync-active-low: 110 $ref: /schemas/types.yaml#/definitions/flag 111 description: 112 Frame sync signals are active on low logic level. 113 If not present, sync signals are active on high level. 114 115 fsl,double-speed-clock: 116 $ref: /schemas/types.yaml#/definitions/flag 117 description: 118 The channel clock is twice the data rate. 119 120 patternProperties: 121 '^fsl,[rt]x-ts-routes$': 122 $ref: /schemas/types.yaml#/definitions/uint32-matrix 123 description: | 124 A list of tuple that indicates the Tx or Rx time-slots routes. 125 items: 126 items: 127 - description: 128 The number of time-slots 129 minimum: 1 130 maximum: 64 131 - description: | 132 The source (Tx) or destination (Rx) serial interface 133 (dt-bindings/soc/qe-fsl,tsa.h defines these values) 134 - 0: No destination 135 - 1: UCC1 136 - 2: UCC2 137 - 3: UCC3 138 - 4: UCC4 139 - 5: UCC5 140 enum: [0, 1, 2, 3, 4, 5] 141 minItems: 1 142 maxItems: 64 143 144 allOf: 145 # If fsl,common-rxtx-pins is present, only 2 clocks are needed. 146 # Else, the 4 clocks must be present. 147 - if: 148 required: 149 - fsl,common-rxtx-pins 150 then: 151 properties: 152 clocks: 153 maxItems: 2 154 clock-names: 155 maxItems: 2 156 else: 157 properties: 158 clocks: 159 minItems: 4 160 clock-names: 161 minItems: 4 162 163 required: 164 - reg 165 - clocks 166 - clock-names 167 168required: 169 - compatible 170 - reg 171 - reg-names 172 - '#address-cells' 173 - '#size-cells' 174 175additionalProperties: false 176 177examples: 178 - | 179 #include <dt-bindings/soc/qe-fsl,tsa.h> 180 181 tsa@ae0 { 182 compatible = "fsl,mpc8321-tsa", "fsl,qe-tsa"; 183 reg = <0xae0 0x10>, 184 <0xc00 0x200>; 185 reg-names = "si_regs", "si_ram"; 186 187 #address-cells = <1>; 188 #size-cells = <0>; 189 190 tdm@0 { 191 /* TDMa */ 192 reg = <0>; 193 194 clocks = <&clk_l1rsynca>, <&clk_l1rclka>; 195 clock-names = "rsync", "rclk"; 196 197 fsl,common-rxtx-pins; 198 fsl,fsync-rising-edge; 199 200 fsl,tx-ts-routes = <2 0>, /* TS 0..1 */ 201 <24 FSL_QE_TSA_UCC4>, /* TS 2..25 */ 202 <1 0>, /* TS 26 */ 203 <5 FSL_QE_TSA_UCC3>; /* TS 27..31 */ 204 205 fsl,rx-ts-routes = <2 0>, /* TS 0..1 */ 206 <24 FSL_QE_TSA_UCC4>, /* 2..25 */ 207 <1 0>, /* TS 26 */ 208 <5 FSL_QE_TSA_UCC3>; /* TS 27..31 */ 209 }; 210 }; 211