xref: /linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml (revision fd7d598270724cc787982ea48bbe17ad383a8b7f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
8
9maintainers:
10  - Herve Codina <herve.codina@bootlin.com>
11
12description:
13  The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one
14  serial controller using the same TDM physical interface routed from TSA.
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - fsl,mpc885-scc-qmc
21          - fsl,mpc866-scc-qmc
22      - const: fsl,cpm1-scc-qmc
23
24  reg:
25    items:
26      - description: SCC (Serial communication controller) register base
27      - description: SCC parameter ram base
28      - description: Dual port ram base
29
30  reg-names:
31    items:
32      - const: scc_regs
33      - const: scc_pram
34      - const: dpram
35
36  interrupts:
37    maxItems: 1
38    description: SCC interrupt line in the CPM interrupt controller
39
40  fsl,tsa-serial:
41    $ref: /schemas/types.yaml#/definitions/phandle-array
42    items:
43      - items:
44          - description: phandle to TSA node
45          - enum: [1, 2, 3]
46            description: |
47              TSA serial interface (dt-bindings/soc/cpm1-fsl,tsa.h defines these
48              values)
49               - 1: SCC2
50               - 2: SCC3
51               - 3: SCC4
52    description:
53      Should be a phandle/number pair. The phandle to TSA node and the TSA
54      serial interface to use.
55
56  '#address-cells':
57    const: 1
58
59  '#size-cells':
60    const: 0
61
62patternProperties:
63  '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
64    description:
65      A channel managed by this controller
66    type: object
67
68    properties:
69      reg:
70        minimum: 0
71        maximum: 63
72        description:
73          The channel number
74
75      fsl,operational-mode:
76        $ref: /schemas/types.yaml#/definitions/string
77        enum: [transparent, hdlc]
78        default: transparent
79        description: |
80          The channel operational mode
81            - hdlc: The channel handles HDLC frames
82            - transparent: The channel handles raw data without any processing
83
84      fsl,reverse-data:
85        $ref: /schemas/types.yaml#/definitions/flag
86        description:
87          The bit order as seen on the channels is reversed,
88          transmitting/receiving the MSB of each octet first.
89          This flag is used only in 'transparent' mode.
90
91      fsl,tx-ts-mask:
92        $ref: /schemas/types.yaml#/definitions/uint64
93        description:
94          Channel assigned Tx time-slots within the Tx time-slots routed by the
95          TSA to this cell.
96
97      fsl,rx-ts-mask:
98        $ref: /schemas/types.yaml#/definitions/uint64
99        description:
100          Channel assigned Rx time-slots within the Rx time-slots routed by the
101          TSA to this cell.
102
103    required:
104      - reg
105      - fsl,tx-ts-mask
106      - fsl,rx-ts-mask
107
108required:
109  - compatible
110  - reg
111  - reg-names
112  - interrupts
113  - fsl,tsa-serial
114  - '#address-cells'
115  - '#size-cells'
116
117additionalProperties: false
118
119examples:
120  - |
121    #include <dt-bindings/soc/cpm1-fsl,tsa.h>
122
123    qmc@a60 {
124        compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
125        reg = <0xa60 0x20>,
126              <0x3f00 0xc0>,
127              <0x2000 0x1000>;
128        reg-names = "scc_regs", "scc_pram", "dpram";
129        interrupts = <27>;
130        interrupt-parent = <&CPM_PIC>;
131
132        #address-cells = <1>;
133        #size-cells = <0>;
134
135        fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;
136
137        channel@16 {
138            /* Ch16 : First 4 even TS from all routed from TSA */
139            reg = <16>;
140            fsl,mode = "transparent";
141            fsl,reverse-data;
142            fsl,tx-ts-mask = <0x00000000 0x000000aa>;
143            fsl,rx-ts-mask = <0x00000000 0x000000aa>;
144        };
145
146        channel@17 {
147            /* Ch17 : First 4 odd TS from all routed from TSA */
148            reg = <17>;
149            fsl,mode = "transparent";
150            fsl,reverse-data;
151            fsl,tx-ts-mask = <0x00000000 0x00000055>;
152            fsl,rx-ts-mask = <0x00000000 0x00000055>;
153        };
154
155        channel@19 {
156            /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
157            reg = <19>;
158            fsl,mode = "hdlc";
159            fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
160            fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
161        };
162    };
163