xref: /linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml (revision 4b660dbd9ee2059850fd30e0df420ca7a38a1856) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PowerQUICC CPM QUICC Multichannel Controller (QMC)
8
9maintainers:
10  - Herve Codina <herve.codina@bootlin.com>
11
12description:
13  The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one
14  serial controller using the same TDM physical interface routed from TSA.
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - fsl,mpc885-scc-qmc
21          - fsl,mpc866-scc-qmc
22      - const: fsl,cpm1-scc-qmc
23
24  reg:
25    items:
26      - description: SCC (Serial communication controller) register base
27      - description: SCC parameter ram base
28      - description: Dual port ram base
29
30  reg-names:
31    items:
32      - const: scc_regs
33      - const: scc_pram
34      - const: dpram
35
36  interrupts:
37    maxItems: 1
38    description: SCC interrupt line in the CPM interrupt controller
39
40  fsl,tsa-serial:
41    $ref: /schemas/types.yaml#/definitions/phandle-array
42    items:
43      - items:
44          - description: phandle to TSA node
45          - enum: [1, 2, 3]
46            description: |
47              TSA serial interface (dt-bindings/soc/cpm1-fsl,tsa.h defines these
48              values)
49               - 1: SCC2
50               - 2: SCC3
51               - 3: SCC4
52    description:
53      Should be a phandle/number pair. The phandle to TSA node and the TSA
54      serial interface to use.
55
56  '#address-cells':
57    const: 1
58
59  '#size-cells':
60    const: 0
61
62patternProperties:
63  '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
64    description:
65      A channel managed by this controller
66    type: object
67    additionalProperties: false
68
69    properties:
70      reg:
71        minimum: 0
72        maximum: 63
73        description:
74          The channel number
75
76      fsl,operational-mode:
77        $ref: /schemas/types.yaml#/definitions/string
78        enum: [transparent, hdlc]
79        default: transparent
80        description: |
81          The channel operational mode
82            - hdlc: The channel handles HDLC frames
83            - transparent: The channel handles raw data without any processing
84
85      fsl,reverse-data:
86        $ref: /schemas/types.yaml#/definitions/flag
87        description:
88          The bit order as seen on the channels is reversed,
89          transmitting/receiving the MSB of each octet first.
90          This flag is used only in 'transparent' mode.
91
92      fsl,tx-ts-mask:
93        $ref: /schemas/types.yaml#/definitions/uint64
94        description:
95          Channel assigned Tx time-slots within the Tx time-slots routed by the
96          TSA to this cell.
97
98      fsl,rx-ts-mask:
99        $ref: /schemas/types.yaml#/definitions/uint64
100        description:
101          Channel assigned Rx time-slots within the Rx time-slots routed by the
102          TSA to this cell.
103
104      compatible:
105        items:
106          - enum:
107              - fsl,mpc885-scc-qmc-hdlc
108              - fsl,mpc866-scc-qmc-hdlc
109          - const: fsl,cpm1-scc-qmc-hdlc
110          - const: fsl,qmc-hdlc
111
112      fsl,framer:
113        $ref: /schemas/types.yaml#/definitions/phandle
114        description:
115          phandle to the framer node. The framer is in charge of an E1/T1 line
116          interface connected to the TDM bus. It can be used to get the E1/T1 line
117          status such as link up/down.
118
119    allOf:
120      - if:
121          properties:
122            compatible:
123              not:
124                contains:
125                  const: fsl,qmc-hdlc
126        then:
127          properties:
128            fsl,framer: false
129
130    required:
131      - reg
132      - fsl,tx-ts-mask
133      - fsl,rx-ts-mask
134
135required:
136  - compatible
137  - reg
138  - reg-names
139  - interrupts
140  - fsl,tsa-serial
141  - '#address-cells'
142  - '#size-cells'
143
144additionalProperties: false
145
146examples:
147  - |
148    #include <dt-bindings/soc/cpm1-fsl,tsa.h>
149
150    qmc@a60 {
151        compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
152        reg = <0xa60 0x20>,
153              <0x3f00 0xc0>,
154              <0x2000 0x1000>;
155        reg-names = "scc_regs", "scc_pram", "dpram";
156        interrupts = <27>;
157        interrupt-parent = <&CPM_PIC>;
158
159        #address-cells = <1>;
160        #size-cells = <0>;
161
162        fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;
163
164        channel@16 {
165            /* Ch16 : First 4 even TS from all routed from TSA */
166            reg = <16>;
167            fsl,operational-mode = "transparent";
168            fsl,reverse-data;
169            fsl,tx-ts-mask = <0x00000000 0x000000aa>;
170            fsl,rx-ts-mask = <0x00000000 0x000000aa>;
171        };
172
173        channel@17 {
174            /* Ch17 : First 4 odd TS from all routed from TSA */
175            reg = <17>;
176            fsl,operational-mode = "transparent";
177            fsl,reverse-data;
178            fsl,tx-ts-mask = <0x00000000 0x00000055>;
179            fsl,rx-ts-mask = <0x00000000 0x00000055>;
180        };
181
182        channel@19 {
183            /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
184            compatible = "fsl,mpc885-scc-qmc-hdlc",
185                         "fsl,cpm1-scc-qmc-hdlc",
186                         "fsl,qmc-hdlc";
187            reg = <19>;
188            fsl,operational-mode = "hdlc";
189            fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
190            fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
191            fsl,framer = <&framer>;
192        };
193    };
194