xref: /linux/Documentation/devicetree/bindings/serial/renesas,scif.yaml (revision 9dbbc3b9d09d6deba9f3b9e1d5b355032ed46a75) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/serial/renesas,scif.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas Serial Communication Interface with FIFO (SCIF)
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12allOf:
13  - $ref: serial.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - renesas,scif-r7s72100     # RZ/A1H
21          - const: renesas,scif           # generic SCIF compatible UART
22
23      - items:
24          - enum:
25              - renesas,scif-r7s9210      # RZ/A2
26
27      - items:
28          - enum:
29              - renesas,scif-r8a7778      # R-Car M1
30              - renesas,scif-r8a7779      # R-Car H1
31          - const: renesas,rcar-gen1-scif # R-Car Gen1
32          - const: renesas,scif           # generic SCIF compatible UART
33
34      - items:
35          - enum:
36              - renesas,scif-r8a7742      # RZ/G1H
37              - renesas,scif-r8a7743      # RZ/G1M
38              - renesas,scif-r8a7744      # RZ/G1N
39              - renesas,scif-r8a7745      # RZ/G1E
40              - renesas,scif-r8a77470     # RZ/G1C
41              - renesas,scif-r8a7790      # R-Car H2
42              - renesas,scif-r8a7791      # R-Car M2-W
43              - renesas,scif-r8a7792      # R-Car V2H
44              - renesas,scif-r8a7793      # R-Car M2-N
45              - renesas,scif-r8a7794      # R-Car E2
46          - const: renesas,rcar-gen2-scif # R-Car Gen2 and RZ/G1
47          - const: renesas,scif           # generic SCIF compatible UART
48
49      - items:
50          - enum:
51              - renesas,scif-r8a774a1     # RZ/G2M
52              - renesas,scif-r8a774b1     # RZ/G2N
53              - renesas,scif-r8a774c0     # RZ/G2E
54              - renesas,scif-r8a774e1     # RZ/G2H
55              - renesas,scif-r8a7795      # R-Car H3
56              - renesas,scif-r8a7796      # R-Car M3-W
57              - renesas,scif-r8a77961     # R-Car M3-W+
58              - renesas,scif-r8a77965     # R-Car M3-N
59              - renesas,scif-r8a77970     # R-Car V3M
60              - renesas,scif-r8a77980     # R-Car V3H
61              - renesas,scif-r8a77990     # R-Car E3
62              - renesas,scif-r8a77995     # R-Car D3
63              - renesas,scif-r8a779a0     # R-Car V3U
64          - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
65          - const: renesas,scif           # generic SCIF compatible UART
66
67      - items:
68          - enum:
69              - renesas,scif-r9a07g044      # RZ/G2{L,LC}
70
71  reg:
72    maxItems: 1
73
74  interrupts:
75    oneOf:
76      - items:
77          - description: A combined interrupt
78      - items:
79          - description: Error interrupt
80          - description: Receive buffer full interrupt
81          - description: Transmit buffer empty interrupt
82          - description: Transmit End interrupt
83      - items:
84          - description: Error interrupt
85          - description: Receive buffer full interrupt
86          - description: Transmit buffer empty interrupt
87          - description: Break interrupt
88          - description: Data Ready interrupt
89          - description: Transmit End interrupt
90
91  interrupt-names:
92    oneOf:
93      - items:
94          - const: eri
95          - const: rxi
96          - const: txi
97          - const: tei
98      - items:
99          - const: eri
100          - const: rxi
101          - const: txi
102          - const: bri
103          - const: dri
104          - const: tei
105
106  clocks:
107    minItems: 1
108    maxItems: 4
109
110  clock-names:
111    minItems: 1
112    maxItems: 4
113    items:
114      enum:
115        - fck # UART functional clock
116        - sck # optional external clock input
117        - brg_int # optional internal clock source for BRG frequency divider
118        - scif_clk # optional external clock source for BRG frequency divider
119
120  power-domains:
121    maxItems: 1
122
123  resets:
124    maxItems: 1
125
126  dmas:
127    minItems: 2
128    maxItems: 4
129    description:
130      Must contain a list of pairs of references to DMA specifiers, one for
131      transmission, and one for reception.
132
133  dma-names:
134    minItems: 2
135    maxItems: 4
136    items:
137      enum:
138        - tx
139        - rx
140
141required:
142  - compatible
143  - reg
144  - interrupts
145  - clocks
146  - clock-names
147  - power-domains
148
149if:
150  properties:
151    compatible:
152      contains:
153        enum:
154          - renesas,rcar-gen2-scif
155          - renesas,rcar-gen3-scif
156then:
157  required:
158    - resets
159
160unevaluatedProperties: false
161
162examples:
163  - |
164    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
165    #include <dt-bindings/interrupt-controller/arm-gic.h>
166    #include <dt-bindings/power/r8a7791-sysc.h>
167    aliases {
168            serial0 = &scif0;
169    };
170
171    scif0: serial@e6e60000 {
172            compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif",
173                         "renesas,scif";
174            reg = <0xe6e60000 64>;
175            interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
176            clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>,
177                     <&scif_clk>;
178            clock-names = "fck", "brg_int", "scif_clk";
179            dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>;
180            dma-names = "tx", "rx", "tx", "rx";
181            power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
182            resets = <&cpg 721>;
183    };
184