1*5b28371fSKartik Rajput# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*5b28371fSKartik Rajput%YAML 1.2 3*5b28371fSKartik Rajput--- 4*5b28371fSKartik Rajput$id: http://devicetree.org/schemas/serial/nvidia,tegra264-utc.yaml# 5*5b28371fSKartik Rajput$schema: http://devicetree.org/meta-schemas/core.yaml# 6*5b28371fSKartik Rajput 7*5b28371fSKartik Rajputtitle: NVIDIA Tegra UTC (UART Trace Controller) client 8*5b28371fSKartik Rajput 9*5b28371fSKartik Rajputmaintainers: 10*5b28371fSKartik Rajput - Kartik Rajput <kkartik@nvidia.com> 11*5b28371fSKartik Rajput - Thierry Reding <thierry.reding@gmail.com> 12*5b28371fSKartik Rajput - Jonathan Hunter <jonathanh@nvidia.com> 13*5b28371fSKartik Rajput 14*5b28371fSKartik Rajputdescription: 15*5b28371fSKartik Rajput Represents a client interface of the Tegra UTC (UART Trace Controller). The 16*5b28371fSKartik Rajput Tegra UTC allows multiple clients within the Tegra SoC to share a physical 17*5b28371fSKartik Rajput UART interface. It supports up to 16 clients. Each client operates as an 18*5b28371fSKartik Rajput independent UART endpoint with a dedicated interrupt and 128-character TX/RX 19*5b28371fSKartik Rajput FIFOs. 20*5b28371fSKartik Rajput 21*5b28371fSKartik Rajput The Tegra UTC clients use 8-N-1 configuration and operates on a baudrate 22*5b28371fSKartik Rajput configured by the bootloader at the controller level. 23*5b28371fSKartik Rajput 24*5b28371fSKartik RajputallOf: 25*5b28371fSKartik Rajput - $ref: serial.yaml# 26*5b28371fSKartik Rajput 27*5b28371fSKartik Rajputproperties: 28*5b28371fSKartik Rajput compatible: 29*5b28371fSKartik Rajput const: nvidia,tegra264-utc 30*5b28371fSKartik Rajput 31*5b28371fSKartik Rajput reg: 32*5b28371fSKartik Rajput items: 33*5b28371fSKartik Rajput - description: TX region. 34*5b28371fSKartik Rajput - description: RX region. 35*5b28371fSKartik Rajput 36*5b28371fSKartik Rajput reg-names: 37*5b28371fSKartik Rajput items: 38*5b28371fSKartik Rajput - const: tx 39*5b28371fSKartik Rajput - const: rx 40*5b28371fSKartik Rajput 41*5b28371fSKartik Rajput interrupts: 42*5b28371fSKartik Rajput maxItems: 1 43*5b28371fSKartik Rajput 44*5b28371fSKartik Rajput tx-threshold: 45*5b28371fSKartik Rajput minimum: 1 46*5b28371fSKartik Rajput maximum: 128 47*5b28371fSKartik Rajput 48*5b28371fSKartik Rajput rx-threshold: 49*5b28371fSKartik Rajput minimum: 1 50*5b28371fSKartik Rajput maximum: 128 51*5b28371fSKartik Rajput 52*5b28371fSKartik Rajputrequired: 53*5b28371fSKartik Rajput - compatible 54*5b28371fSKartik Rajput - reg 55*5b28371fSKartik Rajput - reg-names 56*5b28371fSKartik Rajput - interrupts 57*5b28371fSKartik Rajput - tx-threshold 58*5b28371fSKartik Rajput - rx-threshold 59*5b28371fSKartik Rajput 60*5b28371fSKartik RajputadditionalProperties: false 61*5b28371fSKartik Rajput 62*5b28371fSKartik Rajputexamples: 63*5b28371fSKartik Rajput - | 64*5b28371fSKartik Rajput #include <dt-bindings/interrupt-controller/arm-gic.h> 65*5b28371fSKartik Rajput 66*5b28371fSKartik Rajput tegra_utc: serial@c4e0000 { 67*5b28371fSKartik Rajput compatible = "nvidia,tegra264-utc"; 68*5b28371fSKartik Rajput reg = <0xc4e0000 0x8000>, <0xc4e8000 0x8000>; 69*5b28371fSKartik Rajput reg-names = "tx", "rx"; 70*5b28371fSKartik Rajput interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; 71*5b28371fSKartik Rajput tx-threshold = <4>; 72*5b28371fSKartik Rajput rx-threshold = <4>; 73*5b28371fSKartik Rajput }; 74