xref: /linux/Documentation/devicetree/bindings/serial/lantiq,asc.yaml (revision 378ec25aec5a8444879f8696d580c94950a1f1df) 
1*6f5ff13bSRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*6f5ff13bSRob Herring (Arm)%YAML 1.2
3*6f5ff13bSRob Herring (Arm)---
4*6f5ff13bSRob Herring (Arm)$id: http://devicetree.org/schemas/serial/lantiq,asc.yaml#
5*6f5ff13bSRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml#
6*6f5ff13bSRob Herring (Arm)
7*6f5ff13bSRob Herring (Arm)title: Lantiq SoC ASC serial controller
8*6f5ff13bSRob Herring (Arm)
9*6f5ff13bSRob Herring (Arm)maintainers:
10*6f5ff13bSRob Herring (Arm)  - John Crispin <john@phrozen.org>
11*6f5ff13bSRob Herring (Arm)  - Songjun Wu <songjun.wu@linux.intel.com>
12*6f5ff13bSRob Herring (Arm)
13*6f5ff13bSRob Herring (Arm)allOf:
14*6f5ff13bSRob Herring (Arm)  - $ref: /schemas/serial/serial.yaml#
15*6f5ff13bSRob Herring (Arm)
16*6f5ff13bSRob Herring (Arm)properties:
17*6f5ff13bSRob Herring (Arm)  compatible:
18*6f5ff13bSRob Herring (Arm)    const: lantiq,asc
19*6f5ff13bSRob Herring (Arm)
20*6f5ff13bSRob Herring (Arm)  reg:
21*6f5ff13bSRob Herring (Arm)    maxItems: 1
22*6f5ff13bSRob Herring (Arm)
23*6f5ff13bSRob Herring (Arm)  interrupts:
24*6f5ff13bSRob Herring (Arm)    items:
25*6f5ff13bSRob Herring (Arm)      - description: TX interrupt
26*6f5ff13bSRob Herring (Arm)      - description: RX interrupt
27*6f5ff13bSRob Herring (Arm)      - description: Error interrupt
28*6f5ff13bSRob Herring (Arm)
29*6f5ff13bSRob Herring (Arm)  clocks:
30*6f5ff13bSRob Herring (Arm)    items:
31*6f5ff13bSRob Herring (Arm)      - description: Frequency clock
32*6f5ff13bSRob Herring (Arm)      - description: Gate clock
33*6f5ff13bSRob Herring (Arm)
34*6f5ff13bSRob Herring (Arm)  clock-names:
35*6f5ff13bSRob Herring (Arm)    items:
36*6f5ff13bSRob Herring (Arm)      - const: freq
37*6f5ff13bSRob Herring (Arm)      - const: asc
38*6f5ff13bSRob Herring (Arm)
39*6f5ff13bSRob Herring (Arm)required:
40*6f5ff13bSRob Herring (Arm)  - compatible
41*6f5ff13bSRob Herring (Arm)  - reg
42*6f5ff13bSRob Herring (Arm)  - interrupts
43*6f5ff13bSRob Herring (Arm)
44*6f5ff13bSRob Herring (Arm)unevaluatedProperties: false
45*6f5ff13bSRob Herring (Arm)
46*6f5ff13bSRob Herring (Arm)examples:
47*6f5ff13bSRob Herring (Arm)  - |
48*6f5ff13bSRob Herring (Arm)    #include <dt-bindings/interrupt-controller/mips-gic.h>
49*6f5ff13bSRob Herring (Arm)
50*6f5ff13bSRob Herring (Arm)    serial@16600000 {
51*6f5ff13bSRob Herring (Arm)        compatible = "lantiq,asc";
52*6f5ff13bSRob Herring (Arm)        reg = <0x16600000 0x100000>;
53*6f5ff13bSRob Herring (Arm)        interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
54*6f5ff13bSRob Herring (Arm)                     <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
55*6f5ff13bSRob Herring (Arm)                     <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
56*6f5ff13bSRob Herring (Arm)    };
57