xref: /linux/Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml (revision 011f129fee4bd064a3db30ca1a0139548a619482) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
8
9maintainers:
10  - Fabio Estevam <festevam@gmail.com>
11
12allOf:
13  - $ref: serial.yaml#
14  - $ref: rs485.yaml#
15
16properties:
17  compatible:
18    oneOf:
19      - const: fsl,imx1-uart
20      - const: fsl,imx21-uart
21      - items:
22          - enum:
23              - fsl,imx25-uart
24              - fsl,imx27-uart
25              - fsl,imx31-uart
26              - fsl,imx35-uart
27              - fsl,imx50-uart
28              - fsl,imx51-uart
29              - fsl,imx53-uart
30              - fsl,imx6q-uart
31          - const: fsl,imx21-uart
32      - items:
33          - enum:
34              - fsl,imx6sl-uart
35              - fsl,imx6sll-uart
36              - fsl,imx6sx-uart
37          - const: fsl,imx6q-uart
38          - const: fsl,imx21-uart
39      - items:
40          - enum:
41              - fsl,imx6ul-uart
42              - fsl,imx7d-uart
43              - fsl,imx8mm-uart
44              - fsl,imx8mn-uart
45              - fsl,imx8mp-uart
46              - fsl,imx8mq-uart
47          - const: fsl,imx6q-uart
48
49  reg:
50    maxItems: 1
51
52  clocks:
53    maxItems: 2
54
55  clock-names:
56    items:
57      - const: ipg
58      - const: per
59
60  dmas:
61    items:
62      - description: DMA controller phandle and request line for RX
63      - description: DMA controller phandle and request line for TX
64
65  dma-names:
66    items:
67      - const: rx
68      - const: tx
69
70  interrupts:
71    maxItems: 1
72
73  wakeup-source: true
74
75  fsl,dte-mode:
76    $ref: /schemas/types.yaml#/definitions/flag
77    description: |
78      Indicate the uart works in DTE mode. The uart works in DCE mode by default.
79
80  fsl,inverted-tx:
81    $ref: /schemas/types.yaml#/definitions/flag
82    description: |
83      Indicate that the hardware attached to the peripheral inverts the signal
84      transmitted, and that the peripheral should invert its output using the
85      INVT registers.
86
87  fsl,inverted-rx:
88    $ref: /schemas/types.yaml#/definitions/flag
89    description: |
90      Indicate that the hardware attached to the peripheral inverts the signal
91      received, and that the peripheral should invert its input using the
92      INVR registers.
93
94  fsl,dma-info:
95    $ref: /schemas/types.yaml#/definitions/uint32-array
96    minItems: 2
97    maxItems: 2
98    description: |
99      First cell contains the size of DMA buffer chunks, second cell contains
100      the amount of chunks used for the device. Multiplying both numbers is
101      the total size of memory used for receiving data.
102      When not being configured the system will use default settings, which
103      are sensible for most use cases. If you need low latency processing on
104      slow connections this needs to be configured appropriately.
105
106required:
107  - compatible
108  - reg
109  - clocks
110  - clock-names
111  - interrupts
112
113unevaluatedProperties: false
114
115examples:
116  - |
117    #include <dt-bindings/clock/imx5-clock.h>
118
119    aliases {
120        serial0 = &uart1;
121    };
122
123    uart1: serial@73fbc000 {
124        compatible = "fsl,imx51-uart", "fsl,imx21-uart";
125        reg = <0x73fbc000 0x4000>;
126        interrupts = <31>;
127        clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
128                 <&clks IMX5_CLK_UART1_PER_GATE>;
129        clock-names = "ipg", "per";
130        dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
131        dma-names = "rx", "tx";
132        uart-has-rtscts;
133        fsl,dte-mode;
134    };
135