xref: /linux/Documentation/devicetree/bindings/serial/cdns,uart.yaml (revision 0526b56cbc3c489642bd6a5fe4b718dea7ef0ee8) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence UART Controller
8
9maintainers:
10  - Michal Simek <michal.simek@xilinx.com>
11
12properties:
13  compatible:
14    oneOf:
15      - description: UART controller for Zynq-7xxx SoC
16        items:
17          - const: xlnx,xuartps
18          - const: cdns,uart-r1p8
19      - description: UART controller for Zynq Ultrascale+ MPSoC
20        items:
21          - const: xlnx,zynqmp-uart
22          - const: cdns,uart-r1p12
23
24  reg:
25    maxItems: 1
26
27  interrupts:
28    maxItems: 1
29
30  clocks:
31    maxItems: 2
32
33  clock-names:
34    items:
35      - const: uart_clk
36      - const: pclk
37
38  cts-override:
39    description: |
40      Override the CTS modem status signal. This signal will
41      always be reported as active instead of being obtained
42      from the modem status register. Define this if your serial
43      port does not use this pin.
44    type: boolean
45
46  power-domains:
47    maxItems: 1
48
49required:
50  - compatible
51  - reg
52  - interrupts
53  - clocks
54  - clock-names
55
56allOf:
57  - $ref: serial.yaml#
58  - if:
59      properties:
60        compatible:
61          contains:
62            const: cdns,uart-r1p8
63    then:
64      properties:
65        power-domains: false
66
67unevaluatedProperties: false
68
69examples:
70  - |
71    uart0: serial@e0000000 {
72        compatible = "xlnx,xuartps", "cdns,uart-r1p8";
73        clocks = <&clkc 23>, <&clkc 40>;
74        clock-names = "uart_clk", "pclk";
75        reg = <0xe0000000 0x1000>;
76        interrupts = <0 27 4>;
77    };
78