xref: /linux/Documentation/devicetree/bindings/serial/8250.yaml (revision eec2c477d9f45812193170a30fc12bf7eb75de4c) 
1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter)
8
9maintainers:
10  - devicetree@vger.kernel.org
11
12allOf:
13  - $ref: serial.yaml#
14  - if:
15      anyOf:
16        - required:
17            - aspeed,lpc-io-reg
18        - required:
19            - aspeed,lpc-interrupts
20        - required:
21            - aspeed,sirq-polarity-sense
22    then:
23      properties:
24        compatible:
25          const: aspeed,ast2500-vuart
26  - if:
27      properties:
28        compatible:
29          const: mrvl,mmp-uart
30    then:
31      properties:
32        reg-shift:
33          const: 2
34      required:
35        - reg-shift
36  - if:
37      not:
38        properties:
39          compatible:
40            items:
41              - enum:
42                  - ns8250
43                  - ns16450
44                  - ns16550
45                  - ns16550a
46    then:
47      anyOf:
48        - required: [ clock-frequency ]
49        - required: [ clocks ]
50
51properties:
52  compatible:
53    oneOf:
54      - const: ns8250
55      - const: ns16450
56      - const: ns16550
57      - const: ns16550a
58      - const: ns16850
59      - const: aspeed,ast2400-vuart
60      - const: aspeed,ast2500-vuart
61      - const: intel,xscale-uart
62      - const: mrvl,pxa-uart
63      - const: nuvoton,wpcm450-uart
64      - const: nuvoton,npcm750-uart
65      - const: nvidia,tegra20-uart
66      - const: nxp,lpc3220-uart
67      - items:
68          - enum:
69              - exar,xr16l2552
70              - exar,xr16l2551
71              - exar,xr16l2550
72          - const: ns8250
73      - items:
74          - enum:
75              - altr,16550-FIFO32
76              - altr,16550-FIFO64
77              - altr,16550-FIFO128
78              - fsl,16550-FIFO64
79              - fsl,ns16550
80              - andestech,uart16550
81              - nxp,lpc1850-uart
82              - opencores,uart16550-rtlsvn105
83              - ti,da830-uart
84          - const: ns16550a
85      - items:
86          - enum:
87              - ns16750
88              - cavium,octeon-3860-uart
89              - xlnx,xps-uart16550-2.00.b
90              - ralink,rt2880-uart
91          - enum:
92              - ns16550 # Deprecated, unless the FIFO really is broken
93              - ns16550a
94      - items:
95          - enum:
96              - nuvoton,npcm845-uart
97          - const: nuvoton,npcm750-uart
98      - items:
99          - enum:
100              - ralink,mt7620a-uart
101              - ralink,rt3052-uart
102              - ralink,rt3883-uart
103          - const: ralink,rt2880-uart
104          - enum:
105              - ns16550 # Deprecated, unless the FIFO really is broken
106              - ns16550a
107      - items:
108          - enum:
109              - mediatek,mt7622-btif
110              - mediatek,mt7623-btif
111          - const: mediatek,mtk-btif
112      - items:
113          - const: mrvl,mmp-uart
114          - const: intel,xscale-uart
115      - items:
116          - enum:
117              - nvidia,tegra30-uart
118              - nvidia,tegra114-uart
119              - nvidia,tegra124-uart
120              - nvidia,tegra210-uart
121              - nvidia,tegra186-uart
122              - nvidia,tegra194-uart
123              - nvidia,tegra234-uart
124          - const: nvidia,tegra20-uart
125
126  reg:
127    maxItems: 1
128
129  interrupts:
130    maxItems: 1
131
132  clock-frequency: true
133
134  clocks:
135    maxItems: 1
136
137  resets:
138    maxItems: 1
139
140  current-speed:
141    $ref: /schemas/types.yaml#/definitions/uint32
142    description: The current active speed of the UART.
143
144  reg-offset:
145    $ref: /schemas/types.yaml#/definitions/uint32
146    description: |
147      Offset to apply to the mapbase from the start of the registers.
148
149  reg-shift:
150    description: Quantity to shift the register offsets by.
151
152  reg-io-width:
153    description: |
154      The size (in bytes) of the IO accesses that should be performed on the
155      device. There are some systems that require 32-bit accesses to the
156      UART (e.g. TI davinci).
157
158  used-by-rtas:
159    type: boolean
160    description: |
161      Set to indicate that the port is in use by the OpenFirmware RTAS and
162      should not be registered.
163
164  no-loopback-test:
165    type: boolean
166    description: |
167      Set to indicate that the port does not implement loopback test mode.
168
169  fifo-size:
170    $ref: /schemas/types.yaml#/definitions/uint32
171    description: The fifo size of the UART.
172
173  auto-flow-control:
174    type: boolean
175    description: |
176      One way to enable automatic flow control support. The driver is
177      allowed to detect support for the capability even without this
178      property.
179
180  tx-threshold:
181    description: |
182      Specify the TX FIFO low water indication for parts with programmable
183      TX FIFO thresholds.
184
185  overrun-throttle-ms:
186    description: |
187      How long to pause uart rx when input overrun is encountered.
188
189  rts-gpios: true
190  cts-gpios: true
191  dtr-gpios: true
192  dsr-gpios: true
193  rng-gpios: true
194  dcd-gpios: true
195
196  aspeed,sirq-polarity-sense:
197    $ref: /schemas/types.yaml#/definitions/phandle-array
198    description: |
199      Phandle to aspeed,ast2500-scu compatible syscon alongside register
200      offset and bit number to identify how the SIRQ polarity should be
201      configured. One possible data source is the LPC/eSPI mode bit. Only
202      applicable to aspeed,ast2500-vuart.
203    deprecated: true
204
205  aspeed,lpc-io-reg:
206    $ref: /schemas/types.yaml#/definitions/uint32-array
207    maxItems: 1
208    description: |
209      The VUART LPC address.  Only applicable to aspeed,ast2500-vuart.
210
211  aspeed,lpc-interrupts:
212    $ref: /schemas/types.yaml#/definitions/uint32-array
213    minItems: 2
214    maxItems: 2
215    description: |
216      A 2-cell property describing the VUART SIRQ number and SIRQ
217      polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH).  Only
218      applicable to aspeed,ast2500-vuart.
219
220required:
221  - reg
222  - interrupts
223
224unevaluatedProperties: false
225
226examples:
227  - |
228    serial@80230000 {
229        compatible = "ns8250";
230        reg = <0x80230000 0x100>;
231        interrupts = <10>;
232        reg-shift = <2>;
233        clock-frequency = <48000000>;
234    };
235  - |
236    #include <dt-bindings/gpio/gpio.h>
237    serial@49042000 {
238        compatible = "andestech,uart16550", "ns16550a";
239        reg = <0x49042000 0x400>;
240        interrupts = <80>;
241        clock-frequency = <48000000>;
242        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
243        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
244        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
245        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
246        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
247        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
248    };
249  - |
250    #include <dt-bindings/clock/aspeed-clock.h>
251    #include <dt-bindings/interrupt-controller/irq.h>
252    serial@1e787000 {
253        compatible = "aspeed,ast2500-vuart";
254        reg = <0x1e787000 0x40>;
255        reg-shift = <2>;
256        interrupts = <8>;
257        clocks = <&syscon ASPEED_CLK_APB>;
258        no-loopback-test;
259        aspeed,lpc-io-reg = <0x3f8>;
260        aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
261    };
262
263...
264