xref: /linux/Documentation/devicetree/bindings/serial/8250.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter)
8
9maintainers:
10  - devicetree@vger.kernel.org
11
12allOf:
13  - $ref: serial.yaml#
14  - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15  - if:
16      anyOf:
17        - required:
18            - aspeed,lpc-io-reg
19        - required:
20            - aspeed,lpc-interrupts
21        - required:
22            - aspeed,sirq-polarity-sense
23    then:
24      properties:
25        compatible:
26          const: aspeed,ast2500-vuart
27  - if:
28      properties:
29        compatible:
30          const: mrvl,mmp-uart
31    then:
32      properties:
33        reg-shift:
34          const: 2
35      required:
36        - reg-shift
37  - if:
38      not:
39        properties:
40          compatible:
41            items:
42              - enum:
43                  - ns8250
44                  - ns16450
45                  - ns16550
46                  - ns16550a
47    then:
48      oneOf:
49        - required: [ clock-frequency ]
50        - required: [ clocks ]
51  - if:
52      properties:
53        compatible:
54          contains:
55            const: nxp,lpc1850-uart
56    then:
57      properties:
58        clock-names:
59          items:
60            - const: uartclk
61            - const: reg
62  - if:
63      properties:
64        compatible:
65          contains:
66            const: spacemit,k1-uart
67    then:
68      properties:
69        clock-names:
70          items:
71            - const: core
72            - const: bus
73  - if:
74      properties:
75        compatible:
76          contains:
77            enum:
78              - spacemit,k1-uart
79              - nxp,lpc1850-uart
80    then:
81      required:
82        - clocks
83        - clock-names
84      properties:
85        clocks:
86          minItems: 2
87        clock-names:
88          minItems: 2
89    else:
90      properties:
91        clocks:
92          maxItems: 1
93        clock-names:
94          maxItems: 1
95
96properties:
97  compatible:
98    oneOf:
99      - const: ns8250
100      - const: ns16450
101      - const: ns16550
102      - const: ns16550a
103      - const: ns16850
104      - const: aspeed,ast2400-vuart
105      - const: aspeed,ast2500-vuart
106      - const: intel,xscale-uart
107      - const: mrvl,pxa-uart
108      - const: nuvoton,wpcm450-uart
109      - const: nuvoton,npcm750-uart
110      - const: nvidia,tegra20-uart
111      - const: nxp,lpc3220-uart
112      - items:
113          - enum:
114              - exar,xr16l2552
115              - exar,xr16l2551
116              - exar,xr16l2550
117          - const: ns8250
118      - items:
119          - enum:
120              - altr,16550-FIFO32
121              - altr,16550-FIFO64
122              - altr,16550-FIFO128
123              - fsl,16550-FIFO64
124              - andestech,uart16550
125              - nxp,lpc1850-uart
126              - opencores,uart16550-rtlsvn105
127              - ti,da830-uart
128          - const: ns16550a
129      - items:
130          - enum:
131              - ns16750
132              - fsl,ns16550
133              - cavium,octeon-3860-uart
134              - xlnx,xps-uart16550-2.00.b
135              - ralink,rt2880-uart
136          - enum:
137              - ns16550 # Deprecated, unless the FIFO really is broken
138              - ns16550a
139      - items:
140          - enum:
141              - nuvoton,npcm845-uart
142          - const: nuvoton,npcm750-uart
143      - items:
144          - enum:
145              - ralink,mt7620a-uart
146              - ralink,rt3052-uart
147              - ralink,rt3883-uart
148          - const: ralink,rt2880-uart
149          - enum:
150              - ns16550 # Deprecated, unless the FIFO really is broken
151              - ns16550a
152      - items:
153          - enum:
154              - mediatek,mt7622-btif
155              - mediatek,mt7623-btif
156          - const: mediatek,mtk-btif
157      - items:
158          - enum:
159              - mrvl,mmp-uart
160              - spacemit,k1-uart
161          - const: intel,xscale-uart
162      - items:
163          - enum:
164              - nvidia,tegra30-uart
165              - nvidia,tegra114-uart
166              - nvidia,tegra124-uart
167              - nvidia,tegra210-uart
168              - nvidia,tegra186-uart
169              - nvidia,tegra194-uart
170              - nvidia,tegra234-uart
171          - const: nvidia,tegra20-uart
172
173  reg:
174    maxItems: 1
175
176  interrupts:
177    maxItems: 1
178
179  clock-frequency: true
180
181  clocks:
182    minItems: 1
183    items:
184      - description: The core function clock
185      - description: An optional bus clock
186
187  clock-names:
188    minItems: 1
189    maxItems: 2
190    oneOf:
191      - enum:
192          - main
193          - uart
194      - items:
195          - const: core
196          - const: bus
197      - items:
198          - const: uartclk
199          - const: reg
200
201  dmas:
202    minItems: 1
203    maxItems: 4
204
205  dma-names:
206    minItems: 1
207    maxItems: 4
208
209  resets:
210    maxItems: 1
211
212  current-speed:
213    $ref: /schemas/types.yaml#/definitions/uint32
214    description: The current active speed of the UART.
215
216  reg-offset:
217    $ref: /schemas/types.yaml#/definitions/uint32
218    description: |
219      Offset to apply to the mapbase from the start of the registers.
220
221  reg-shift:
222    description: Quantity to shift the register offsets by.
223
224  reg-io-width:
225    description: |
226      The size (in bytes) of the IO accesses that should be performed on the
227      device. There are some systems that require 32-bit accesses to the
228      UART (e.g. TI davinci).
229
230  used-by-rtas:
231    type: boolean
232    description: |
233      Set to indicate that the port is in use by the OpenFirmware RTAS and
234      should not be registered.
235
236  no-loopback-test:
237    type: boolean
238    description: |
239      Set to indicate that the port does not implement loopback test mode.
240
241  fifo-size:
242    $ref: /schemas/types.yaml#/definitions/uint32
243    description: The fifo size of the UART.
244
245  auto-flow-control:
246    type: boolean
247    description: |
248      One way to enable automatic flow control support. The driver is
249      allowed to detect support for the capability even without this
250      property.
251
252  tx-threshold:
253    description: |
254      Specify the TX FIFO low water indication for parts with programmable
255      TX FIFO thresholds.
256
257  overrun-throttle-ms:
258    description: |
259      How long to pause uart rx when input overrun is encountered.
260
261  rts-gpios: true
262  cts-gpios: true
263  dtr-gpios: true
264  dsr-gpios: true
265  rng-gpios: true
266  dcd-gpios: true
267
268  aspeed,sirq-polarity-sense:
269    $ref: /schemas/types.yaml#/definitions/phandle-array
270    description: |
271      Phandle to aspeed,ast2500-scu compatible syscon alongside register
272      offset and bit number to identify how the SIRQ polarity should be
273      configured. One possible data source is the LPC/eSPI mode bit. Only
274      applicable to aspeed,ast2500-vuart.
275    deprecated: true
276
277  aspeed,lpc-io-reg:
278    $ref: /schemas/types.yaml#/definitions/uint32-array
279    maxItems: 1
280    description: |
281      The VUART LPC address.  Only applicable to aspeed,ast2500-vuart.
282
283  aspeed,lpc-interrupts:
284    $ref: /schemas/types.yaml#/definitions/uint32-array
285    minItems: 2
286    maxItems: 2
287    description: |
288      A 2-cell property describing the VUART SIRQ number and SIRQ
289      polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH).  Only
290      applicable to aspeed,ast2500-vuart.
291
292required:
293  - reg
294  - interrupts
295
296unevaluatedProperties: false
297
298examples:
299  - |
300    serial@80230000 {
301        compatible = "ns8250";
302        reg = <0x80230000 0x100>;
303        interrupts = <10>;
304        reg-shift = <2>;
305        clock-frequency = <48000000>;
306    };
307  - |
308    #include <dt-bindings/gpio/gpio.h>
309    serial@49042000 {
310        compatible = "andestech,uart16550", "ns16550a";
311        reg = <0x49042000 0x400>;
312        interrupts = <80>;
313        clock-frequency = <48000000>;
314        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
315        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
316        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
317        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
318        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
319        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
320    };
321  - |
322    #include <dt-bindings/clock/aspeed-clock.h>
323    #include <dt-bindings/interrupt-controller/irq.h>
324    serial@1e787000 {
325        compatible = "aspeed,ast2500-vuart";
326        reg = <0x1e787000 0x40>;
327        reg-shift = <2>;
328        interrupts = <8>;
329        clocks = <&syscon ASPEED_CLK_APB>;
330        no-loopback-test;
331        aspeed,lpc-io-reg = <0x3f8>;
332        aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
333    };
334
335...
336