xref: /linux/Documentation/devicetree/bindings/serial/8250.yaml (revision d9a0788093565c300f7c8dd034dbfa6ac4da9aa6) 
1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter)
8
9maintainers:
10  - devicetree@vger.kernel.org
11
12allOf:
13  - $ref: serial.yaml#
14  - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15  - if:
16      anyOf:
17        - required:
18            - aspeed,lpc-io-reg
19        - required:
20            - aspeed,lpc-interrupts
21        - required:
22            - aspeed,sirq-polarity-sense
23    then:
24      properties:
25        compatible:
26          const: aspeed,ast2500-vuart
27  - if:
28      properties:
29        compatible:
30          const: mrvl,mmp-uart
31    then:
32      properties:
33        reg-shift:
34          const: 2
35      required:
36        - reg-shift
37  - if:
38      not:
39        properties:
40          compatible:
41            items:
42              - enum:
43                  - ns8250
44                  - ns16450
45                  - ns16550
46                  - ns16550a
47    then:
48      anyOf:
49        - required: [ clock-frequency ]
50        - required: [ clocks ]
51
52properties:
53  compatible:
54    oneOf:
55      - const: ns8250
56      - const: ns16450
57      - const: ns16550
58      - const: ns16550a
59      - const: ns16850
60      - const: aspeed,ast2400-vuart
61      - const: aspeed,ast2500-vuart
62      - const: intel,xscale-uart
63      - const: mrvl,pxa-uart
64      - const: nuvoton,wpcm450-uart
65      - const: nuvoton,npcm750-uart
66      - const: nvidia,tegra20-uart
67      - const: nxp,lpc3220-uart
68      - items:
69          - enum:
70              - exar,xr16l2552
71              - exar,xr16l2551
72              - exar,xr16l2550
73          - const: ns8250
74      - items:
75          - enum:
76              - altr,16550-FIFO32
77              - altr,16550-FIFO64
78              - altr,16550-FIFO128
79              - fsl,16550-FIFO64
80              - andestech,uart16550
81              - nxp,lpc1850-uart
82              - opencores,uart16550-rtlsvn105
83              - ti,da830-uart
84          - const: ns16550a
85      - items:
86          - enum:
87              - ns16750
88              - fsl,ns16550
89              - cavium,octeon-3860-uart
90              - xlnx,xps-uart16550-2.00.b
91              - ralink,rt2880-uart
92          - enum:
93              - ns16550 # Deprecated, unless the FIFO really is broken
94              - ns16550a
95      - items:
96          - enum:
97              - nuvoton,npcm845-uart
98          - const: nuvoton,npcm750-uart
99      - items:
100          - enum:
101              - ralink,mt7620a-uart
102              - ralink,rt3052-uart
103              - ralink,rt3883-uart
104          - const: ralink,rt2880-uart
105          - enum:
106              - ns16550 # Deprecated, unless the FIFO really is broken
107              - ns16550a
108      - items:
109          - enum:
110              - mediatek,mt7622-btif
111              - mediatek,mt7623-btif
112          - const: mediatek,mtk-btif
113      - items:
114          - enum:
115              - mrvl,mmp-uart
116              - spacemit,k1-uart
117          - const: intel,xscale-uart
118      - items:
119          - enum:
120              - nvidia,tegra30-uart
121              - nvidia,tegra114-uart
122              - nvidia,tegra124-uart
123              - nvidia,tegra210-uart
124              - nvidia,tegra186-uart
125              - nvidia,tegra194-uart
126              - nvidia,tegra234-uart
127          - const: nvidia,tegra20-uart
128
129  reg:
130    maxItems: 1
131
132  interrupts:
133    maxItems: 1
134
135  clock-frequency: true
136
137  clocks:
138    minItems: 1
139    items:
140      - description: The core function clock
141      - description: An optional bus clock
142
143  clock-names:
144    minItems: 1
145    items:
146      - const: core
147      - const: bus
148
149  resets:
150    maxItems: 1
151
152  current-speed:
153    $ref: /schemas/types.yaml#/definitions/uint32
154    description: The current active speed of the UART.
155
156  reg-offset:
157    $ref: /schemas/types.yaml#/definitions/uint32
158    description: |
159      Offset to apply to the mapbase from the start of the registers.
160
161  reg-shift:
162    description: Quantity to shift the register offsets by.
163
164  reg-io-width:
165    description: |
166      The size (in bytes) of the IO accesses that should be performed on the
167      device. There are some systems that require 32-bit accesses to the
168      UART (e.g. TI davinci).
169
170  used-by-rtas:
171    type: boolean
172    description: |
173      Set to indicate that the port is in use by the OpenFirmware RTAS and
174      should not be registered.
175
176  no-loopback-test:
177    type: boolean
178    description: |
179      Set to indicate that the port does not implement loopback test mode.
180
181  fifo-size:
182    $ref: /schemas/types.yaml#/definitions/uint32
183    description: The fifo size of the UART.
184
185  auto-flow-control:
186    type: boolean
187    description: |
188      One way to enable automatic flow control support. The driver is
189      allowed to detect support for the capability even without this
190      property.
191
192  tx-threshold:
193    description: |
194      Specify the TX FIFO low water indication for parts with programmable
195      TX FIFO thresholds.
196
197  overrun-throttle-ms:
198    description: |
199      How long to pause uart rx when input overrun is encountered.
200
201  rts-gpios: true
202  cts-gpios: true
203  dtr-gpios: true
204  dsr-gpios: true
205  rng-gpios: true
206  dcd-gpios: true
207
208  aspeed,sirq-polarity-sense:
209    $ref: /schemas/types.yaml#/definitions/phandle-array
210    description: |
211      Phandle to aspeed,ast2500-scu compatible syscon alongside register
212      offset and bit number to identify how the SIRQ polarity should be
213      configured. One possible data source is the LPC/eSPI mode bit. Only
214      applicable to aspeed,ast2500-vuart.
215    deprecated: true
216
217  aspeed,lpc-io-reg:
218    $ref: /schemas/types.yaml#/definitions/uint32-array
219    maxItems: 1
220    description: |
221      The VUART LPC address.  Only applicable to aspeed,ast2500-vuart.
222
223  aspeed,lpc-interrupts:
224    $ref: /schemas/types.yaml#/definitions/uint32-array
225    minItems: 2
226    maxItems: 2
227    description: |
228      A 2-cell property describing the VUART SIRQ number and SIRQ
229      polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH).  Only
230      applicable to aspeed,ast2500-vuart.
231
232required:
233  - reg
234  - interrupts
235
236if:
237  properties:
238    compatible:
239      contains:
240        const: spacemit,k1-uart
241then:
242  required: [clock-names]
243  properties:
244    clocks:
245      minItems: 2
246    clock-names:
247      minItems: 2
248else:
249  properties:
250    clocks:
251      maxItems: 1
252    clock-names:
253      maxItems: 1
254
255unevaluatedProperties: false
256
257examples:
258  - |
259    serial@80230000 {
260        compatible = "ns8250";
261        reg = <0x80230000 0x100>;
262        interrupts = <10>;
263        reg-shift = <2>;
264        clock-frequency = <48000000>;
265    };
266  - |
267    #include <dt-bindings/gpio/gpio.h>
268    serial@49042000 {
269        compatible = "andestech,uart16550", "ns16550a";
270        reg = <0x49042000 0x400>;
271        interrupts = <80>;
272        clock-frequency = <48000000>;
273        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
274        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
275        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
276        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
277        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
278        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
279    };
280  - |
281    #include <dt-bindings/clock/aspeed-clock.h>
282    #include <dt-bindings/interrupt-controller/irq.h>
283    serial@1e787000 {
284        compatible = "aspeed,ast2500-vuart";
285        reg = <0x1e787000 0x40>;
286        reg-shift = <2>;
287        interrupts = <8>;
288        clocks = <&syscon ASPEED_CLK_APB>;
289        no-loopback-test;
290        aspeed,lpc-io-reg = <0x3f8>;
291        aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
292    };
293
294...
295