xref: /linux/Documentation/devicetree/bindings/serial/8250.yaml (revision d5dd580deb54483cce0cb5bbe3f1a132a28c767d) 
1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter) bindings
8
9maintainers:
10  - devicetree@vger.kernel.org
11
12allOf:
13  - $ref: serial.yaml#
14  - if:
15      anyOf:
16        - required:
17            - aspeed,lpc-io-reg
18        - required:
19            - aspeed,lpc-interrupts
20        - required:
21            - aspeed,sirq-polarity-sense
22    then:
23      properties:
24        compatible:
25          const: aspeed,ast2500-vuart
26  - if:
27      properties:
28        compatible:
29          const: mrvl,mmp-uart
30    then:
31      properties:
32        reg-shift:
33          const: 2
34      required:
35        - reg-shift
36  - if:
37      not:
38        properties:
39          compatible:
40            items:
41              - enum:
42                  - ns8250
43                  - ns16450
44                  - ns16550
45                  - ns16550a
46    then:
47      anyOf:
48        - required: [ clock-frequency ]
49        - required: [ clocks ]
50
51properties:
52  compatible:
53    oneOf:
54      - const: ns8250
55      - const: ns16450
56      - const: ns16550
57      - const: ns16550a
58      - const: ns16850
59      - const: aspeed,ast2400-vuart
60      - const: aspeed,ast2500-vuart
61      - const: intel,xscale-uart
62      - const: mrvl,pxa-uart
63      - const: nuvoton,wpcm450-uart
64      - const: nuvoton,npcm750-uart
65      - const: nvidia,tegra20-uart
66      - const: nxp,lpc3220-uart
67      - items:
68          - enum:
69              - exar,xr16l2552
70              - exar,xr16l2551
71              - exar,xr16l2550
72          - const: ns8250
73      - items:
74          - enum:
75              - altr,16550-FIFO32
76              - altr,16550-FIFO64
77              - altr,16550-FIFO128
78              - fsl,16550-FIFO64
79              - fsl,ns16550
80              - andestech,uart16550
81              - nxp,lpc1850-uart
82              - opencores,uart16550-rtlsvn105
83              - ti,da830-uart
84          - const: ns16550a
85      - items:
86          - enum:
87              - ns16750
88              - cavium,octeon-3860-uart
89              - xlnx,xps-uart16550-2.00.b
90              - ralink,rt2880-uart
91          - enum:
92              - ns16550 # Deprecated, unless the FIFO really is broken
93              - ns16550a
94      - items:
95          - enum:
96              - ralink,mt7620a-uart
97              - ralink,rt3052-uart
98              - ralink,rt3883-uart
99          - const: ralink,rt2880-uart
100          - enum:
101              - ns16550 # Deprecated, unless the FIFO really is broken
102              - ns16550a
103      - items:
104          - enum:
105              - mediatek,mt7622-btif
106              - mediatek,mt7623-btif
107          - const: mediatek,mtk-btif
108      - items:
109          - const: mrvl,mmp-uart
110          - const: intel,xscale-uart
111      - items:
112          - enum:
113              - nvidia,tegra30-uart
114              - nvidia,tegra114-uart
115              - nvidia,tegra124-uart
116              - nvidia,tegra186-uart
117              - nvidia,tegra194-uart
118              - nvidia,tegra210-uart
119          - const: nvidia,tegra20-uart
120
121  reg:
122    maxItems: 1
123
124  interrupts:
125    maxItems: 1
126
127  clock-frequency: true
128
129  clocks:
130    maxItems: 1
131
132  resets:
133    maxItems: 1
134
135  current-speed:
136    $ref: /schemas/types.yaml#/definitions/uint32
137    description: The current active speed of the UART.
138
139  reg-offset:
140    description: |
141      Offset to apply to the mapbase from the start of the registers.
142
143  reg-shift:
144    description: Quantity to shift the register offsets by.
145
146  reg-io-width:
147    description: |
148      The size (in bytes) of the IO accesses that should be performed on the
149      device. There are some systems that require 32-bit accesses to the
150      UART (e.g. TI davinci).
151
152  used-by-rtas:
153    type: boolean
154    description: |
155      Set to indicate that the port is in use by the OpenFirmware RTAS and
156      should not be registered.
157
158  no-loopback-test:
159    type: boolean
160    description: |
161      Set to indicate that the port does not implement loopback test mode.
162
163  fifo-size:
164    $ref: /schemas/types.yaml#/definitions/uint32
165    description: The fifo size of the UART.
166
167  auto-flow-control:
168    type: boolean
169    description: |
170      One way to enable automatic flow control support. The driver is
171      allowed to detect support for the capability even without this
172      property.
173
174  tx-threshold:
175    description: |
176      Specify the TX FIFO low water indication for parts with programmable
177      TX FIFO thresholds.
178
179  overrun-throttle-ms:
180    description: |
181      How long to pause uart rx when input overrun is encountered.
182
183  rts-gpios: true
184  cts-gpios: true
185  dtr-gpios: true
186  dsr-gpios: true
187  rng-gpios: true
188  dcd-gpios: true
189
190  aspeed,sirq-polarity-sense:
191    $ref: /schemas/types.yaml#/definitions/phandle-array
192    description: |
193      Phandle to aspeed,ast2500-scu compatible syscon alongside register
194      offset and bit number to identify how the SIRQ polarity should be
195      configured. One possible data source is the LPC/eSPI mode bit. Only
196      applicable to aspeed,ast2500-vuart.
197    deprecated: true
198
199  aspeed,lpc-io-reg:
200    $ref: '/schemas/types.yaml#/definitions/uint32'
201    description: |
202      The VUART LPC address.  Only applicable to aspeed,ast2500-vuart.
203
204  aspeed,lpc-interrupts:
205    $ref: "/schemas/types.yaml#/definitions/uint32-array"
206    minItems: 2
207    maxItems: 2
208    description: |
209      A 2-cell property describing the VUART SIRQ number and SIRQ
210      polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH).  Only
211      applicable to aspeed,ast2500-vuart.
212
213required:
214  - reg
215  - interrupts
216
217unevaluatedProperties: false
218
219examples:
220  - |
221    serial@80230000 {
222        compatible = "ns8250";
223        reg = <0x80230000 0x100>;
224        interrupts = <10>;
225        reg-shift = <2>;
226        clock-frequency = <48000000>;
227    };
228  - |
229    #include <dt-bindings/gpio/gpio.h>
230    serial@49042000 {
231        compatible = "andestech,uart16550", "ns16550a";
232        reg = <0x49042000 0x400>;
233        interrupts = <80>;
234        clock-frequency = <48000000>;
235        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
236        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
237        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
238        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
239        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
240        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
241    };
242  - |
243    #include <dt-bindings/clock/aspeed-clock.h>
244    #include <dt-bindings/interrupt-controller/irq.h>
245    serial@1e787000 {
246        compatible = "aspeed,ast2500-vuart";
247        reg = <0x1e787000 0x40>;
248        reg-shift = <2>;
249        interrupts = <8>;
250        clocks = <&syscon ASPEED_CLK_APB>;
251        no-loopback-test;
252        aspeed,lpc-io-reg = <0x3f8>;
253        aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
254    };
255
256...
257