1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk> 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/serial/8250.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: UART (Universal Asynchronous Receiver/Transmitter) 8 9maintainers: 10 - devicetree@vger.kernel.org 11 12allOf: 13 - $ref: serial.yaml# 14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# 15 - if: 16 anyOf: 17 - required: 18 - aspeed,lpc-io-reg 19 - required: 20 - aspeed,lpc-interrupts 21 - required: 22 - aspeed,sirq-polarity-sense 23 then: 24 properties: 25 compatible: 26 const: aspeed,ast2500-vuart 27 - if: 28 properties: 29 compatible: 30 const: mrvl,mmp-uart 31 then: 32 properties: 33 reg-shift: 34 const: 2 35 required: 36 - reg-shift 37 - if: 38 not: 39 properties: 40 compatible: 41 items: 42 - enum: 43 - ns8250 44 - ns16450 45 - ns16550 46 - ns16550a 47 then: 48 oneOf: 49 - required: [ clock-frequency ] 50 - required: [ clocks ] 51 - if: 52 properties: 53 compatible: 54 contains: 55 const: nxp,lpc1850-uart 56 then: 57 properties: 58 clock-names: 59 items: 60 - const: uartclk 61 - const: reg 62 - if: 63 properties: 64 compatible: 65 contains: 66 const: spacemit,k1-uart 67 then: 68 properties: 69 clock-names: 70 items: 71 - const: core 72 - const: bus 73 - if: 74 properties: 75 compatible: 76 contains: 77 enum: 78 - spacemit,k1-uart 79 - nxp,lpc1850-uart 80 then: 81 required: 82 - clocks 83 - clock-names 84 properties: 85 clocks: 86 minItems: 2 87 clock-names: 88 minItems: 2 89 else: 90 properties: 91 clocks: 92 maxItems: 1 93 clock-names: 94 maxItems: 1 95 96properties: 97 compatible: 98 oneOf: 99 - const: ns8250 100 - const: ns16450 101 - const: ns16550 102 - const: ns16550a 103 - const: ns16850 104 - const: aspeed,ast2400-vuart 105 - const: aspeed,ast2500-vuart 106 - const: intel,xscale-uart 107 - const: mrvl,pxa-uart 108 - const: nuvoton,wpcm450-uart 109 - const: nuvoton,npcm750-uart 110 - const: nvidia,tegra20-uart 111 - const: nxp,lpc3220-uart 112 - items: 113 - enum: 114 - exar,xr16l2552 115 - exar,xr16l2551 116 - exar,xr16l2550 117 - const: ns8250 118 - items: 119 - enum: 120 - altr,16550-FIFO32 121 - altr,16550-FIFO64 122 - altr,16550-FIFO128 123 - fsl,16550-FIFO64 124 - andestech,uart16550 125 - nxp,lpc1850-uart 126 - opencores,uart16550-rtlsvn105 127 - ti,da830-uart 128 - loongson,ls2k0500-uart 129 - loongson,ls2k1500-uart 130 - const: ns16550a 131 - items: 132 - enum: 133 - ns16750 134 - fsl,ns16550 135 - cavium,octeon-3860-uart 136 - xlnx,xps-uart16550-2.00.b 137 - ralink,rt2880-uart 138 - enum: 139 - ns16550 # Deprecated, unless the FIFO really is broken 140 - ns16550a 141 - items: 142 - enum: 143 - nuvoton,npcm845-uart 144 - const: nuvoton,npcm750-uart 145 - items: 146 - enum: 147 - ralink,mt7620a-uart 148 - ralink,rt3052-uart 149 - ralink,rt3883-uart 150 - const: ralink,rt2880-uart 151 - enum: 152 - ns16550 # Deprecated, unless the FIFO really is broken 153 - ns16550a 154 - items: 155 - enum: 156 - mediatek,mt7622-btif 157 - mediatek,mt7623-btif 158 - const: mediatek,mtk-btif 159 - items: 160 - enum: 161 - mrvl,mmp-uart 162 - spacemit,k1-uart 163 - spacemit,k3-uart 164 - const: intel,xscale-uart 165 - items: 166 - enum: 167 - nvidia,tegra30-uart 168 - nvidia,tegra114-uart 169 - nvidia,tegra124-uart 170 - nvidia,tegra210-uart 171 - nvidia,tegra186-uart 172 - nvidia,tegra194-uart 173 - nvidia,tegra234-uart 174 - const: nvidia,tegra20-uart 175 - items: 176 - enum: 177 - loongson,ls2k1000-uart 178 - const: loongson,ls2k0500-uart 179 - const: ns16550a 180 - items: 181 - enum: 182 - loongson,ls3a5000-uart 183 - loongson,ls3a6000-uart 184 - loongson,ls2k2000-uart 185 - const: loongson,ls2k1500-uart 186 - const: ns16550a 187 188 reg: 189 maxItems: 1 190 191 interrupts: 192 maxItems: 1 193 194 clock-frequency: true 195 196 clocks: 197 minItems: 1 198 items: 199 - description: The core function clock 200 - description: An optional bus clock 201 202 clock-names: 203 minItems: 1 204 maxItems: 2 205 oneOf: 206 - enum: 207 - main 208 - uart 209 - items: 210 - const: core 211 - const: bus 212 - items: 213 - const: uartclk 214 - const: reg 215 216 dmas: 217 minItems: 1 218 maxItems: 4 219 220 dma-names: 221 minItems: 1 222 maxItems: 4 223 224 resets: 225 maxItems: 1 226 227 current-speed: 228 $ref: /schemas/types.yaml#/definitions/uint32 229 description: The current active speed of the UART. 230 231 reg-offset: 232 $ref: /schemas/types.yaml#/definitions/uint32 233 description: | 234 Offset to apply to the mapbase from the start of the registers. 235 236 reg-shift: 237 description: Quantity to shift the register offsets by. 238 239 reg-io-width: 240 description: | 241 The size (in bytes) of the IO accesses that should be performed on the 242 device. There are some systems that require 32-bit accesses to the 243 UART (e.g. TI davinci). 244 245 used-by-rtas: 246 type: boolean 247 description: | 248 Set to indicate that the port is in use by the OpenFirmware RTAS and 249 should not be registered. 250 251 no-loopback-test: 252 type: boolean 253 description: | 254 Set to indicate that the port does not implement loopback test mode. 255 256 fifo-size: 257 $ref: /schemas/types.yaml#/definitions/uint32 258 description: The fifo size of the UART. 259 260 auto-flow-control: 261 type: boolean 262 description: | 263 One way to enable automatic flow control support. The driver is 264 allowed to detect support for the capability even without this 265 property. 266 267 tx-threshold: 268 description: | 269 Specify the TX FIFO low water indication for parts with programmable 270 TX FIFO thresholds. 271 272 overrun-throttle-ms: 273 description: | 274 How long to pause uart rx when input overrun is encountered. 275 276 rts-gpios: true 277 cts-gpios: true 278 dtr-gpios: true 279 dsr-gpios: true 280 rng-gpios: true 281 dcd-gpios: true 282 283 aspeed,sirq-polarity-sense: 284 $ref: /schemas/types.yaml#/definitions/phandle-array 285 description: | 286 Phandle to aspeed,ast2500-scu compatible syscon alongside register 287 offset and bit number to identify how the SIRQ polarity should be 288 configured. One possible data source is the LPC/eSPI mode bit. Only 289 applicable to aspeed,ast2500-vuart. 290 deprecated: true 291 292 aspeed,lpc-io-reg: 293 $ref: /schemas/types.yaml#/definitions/uint32-array 294 maxItems: 1 295 description: | 296 The VUART LPC address. Only applicable to aspeed,ast2500-vuart. 297 298 aspeed,lpc-interrupts: 299 $ref: /schemas/types.yaml#/definitions/uint32-array 300 minItems: 2 301 maxItems: 2 302 description: | 303 A 2-cell property describing the VUART SIRQ number and SIRQ 304 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only 305 applicable to aspeed,ast2500-vuart. 306 307required: 308 - reg 309 - interrupts 310 311unevaluatedProperties: false 312 313examples: 314 - | 315 serial@80230000 { 316 compatible = "ns8250"; 317 reg = <0x80230000 0x100>; 318 interrupts = <10>; 319 reg-shift = <2>; 320 clock-frequency = <48000000>; 321 }; 322 - | 323 #include <dt-bindings/gpio/gpio.h> 324 serial@49042000 { 325 compatible = "andestech,uart16550", "ns16550a"; 326 reg = <0x49042000 0x400>; 327 interrupts = <80>; 328 clock-frequency = <48000000>; 329 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; 330 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; 331 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 332 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 333 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 334 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 335 }; 336 - | 337 #include <dt-bindings/clock/aspeed-clock.h> 338 #include <dt-bindings/interrupt-controller/irq.h> 339 serial@1e787000 { 340 compatible = "aspeed,ast2500-vuart"; 341 reg = <0x1e787000 0x40>; 342 reg-shift = <2>; 343 interrupts = <8>; 344 clocks = <&syscon ASPEED_CLK_APB>; 345 no-loopback-test; 346 aspeed,lpc-io-reg = <0x3f8>; 347 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 348 }; 349 350... 351