xref: /linux/Documentation/devicetree/bindings/serial/8250.yaml (revision 770ba14bd7fca8a25e6f73ac25dc2cd1377be6fa) 
1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter)
8
9maintainers:
10  - devicetree@vger.kernel.org
11
12allOf:
13  - $ref: serial.yaml#
14  - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15  - if:
16      anyOf:
17        - required:
18            - aspeed,lpc-io-reg
19        - required:
20            - aspeed,lpc-interrupts
21        - required:
22            - aspeed,sirq-polarity-sense
23    then:
24      properties:
25        compatible:
26          const: aspeed,ast2500-vuart
27  - if:
28      properties:
29        compatible:
30          const: mrvl,mmp-uart
31    then:
32      properties:
33        reg-shift:
34          const: 2
35      required:
36        - reg-shift
37  - if:
38      not:
39        properties:
40          compatible:
41            items:
42              - enum:
43                  - ns8250
44                  - ns16450
45                  - ns16550
46                  - ns16550a
47    then:
48      anyOf:
49        - required: [ clock-frequency ]
50        - required: [ clocks ]
51
52properties:
53  compatible:
54    oneOf:
55      - const: ns8250
56      - const: ns16450
57      - const: ns16550
58      - const: ns16550a
59      - const: ns16850
60      - const: aspeed,ast2400-vuart
61      - const: aspeed,ast2500-vuart
62      - const: intel,xscale-uart
63      - const: mrvl,pxa-uart
64      - const: nuvoton,wpcm450-uart
65      - const: nuvoton,npcm750-uart
66      - const: nuvoton,npcm845-uart
67      - const: nvidia,tegra20-uart
68      - const: nxp,lpc3220-uart
69      - items:
70          - enum:
71              - exar,xr16l2552
72              - exar,xr16l2551
73              - exar,xr16l2550
74          - const: ns8250
75      - items:
76          - enum:
77              - altr,16550-FIFO32
78              - altr,16550-FIFO64
79              - altr,16550-FIFO128
80              - fsl,16550-FIFO64
81              - fsl,ns16550
82              - andestech,uart16550
83              - nxp,lpc1850-uart
84              - opencores,uart16550-rtlsvn105
85              - ti,da830-uart
86          - const: ns16550a
87      - items:
88          - enum:
89              - ns16750
90              - cavium,octeon-3860-uart
91              - xlnx,xps-uart16550-2.00.b
92              - ralink,rt2880-uart
93          - enum:
94              - ns16550 # Deprecated, unless the FIFO really is broken
95              - ns16550a
96      - items:
97          - enum:
98              - ralink,mt7620a-uart
99              - ralink,rt3052-uart
100              - ralink,rt3883-uart
101          - const: ralink,rt2880-uart
102          - enum:
103              - ns16550 # Deprecated, unless the FIFO really is broken
104              - ns16550a
105      - items:
106          - enum:
107              - mediatek,mt7622-btif
108              - mediatek,mt7623-btif
109          - const: mediatek,mtk-btif
110      - items:
111          - const: mrvl,mmp-uart
112          - const: intel,xscale-uart
113      - items:
114          - enum:
115              - nvidia,tegra30-uart
116              - nvidia,tegra114-uart
117              - nvidia,tegra124-uart
118              - nvidia,tegra210-uart
119              - nvidia,tegra186-uart
120              - nvidia,tegra194-uart
121              - nvidia,tegra234-uart
122          - const: nvidia,tegra20-uart
123
124  reg:
125    maxItems: 1
126
127  interrupts:
128    maxItems: 1
129
130  clock-frequency: true
131
132  clocks:
133    maxItems: 1
134
135  resets:
136    maxItems: 1
137
138  current-speed:
139    $ref: /schemas/types.yaml#/definitions/uint32
140    description: The current active speed of the UART.
141
142  reg-offset:
143    $ref: /schemas/types.yaml#/definitions/uint32
144    description: |
145      Offset to apply to the mapbase from the start of the registers.
146
147  reg-shift:
148    description: Quantity to shift the register offsets by.
149
150  reg-io-width:
151    description: |
152      The size (in bytes) of the IO accesses that should be performed on the
153      device. There are some systems that require 32-bit accesses to the
154      UART (e.g. TI davinci).
155
156  used-by-rtas:
157    type: boolean
158    description: |
159      Set to indicate that the port is in use by the OpenFirmware RTAS and
160      should not be registered.
161
162  no-loopback-test:
163    type: boolean
164    description: |
165      Set to indicate that the port does not implement loopback test mode.
166
167  fifo-size:
168    $ref: /schemas/types.yaml#/definitions/uint32
169    description: The fifo size of the UART.
170
171  auto-flow-control:
172    type: boolean
173    description: |
174      One way to enable automatic flow control support. The driver is
175      allowed to detect support for the capability even without this
176      property.
177
178  tx-threshold:
179    description: |
180      Specify the TX FIFO low water indication for parts with programmable
181      TX FIFO thresholds.
182
183  overrun-throttle-ms:
184    description: |
185      How long to pause uart rx when input overrun is encountered.
186
187  rts-gpios: true
188  cts-gpios: true
189  dtr-gpios: true
190  dsr-gpios: true
191  rng-gpios: true
192  dcd-gpios: true
193
194  aspeed,sirq-polarity-sense:
195    $ref: /schemas/types.yaml#/definitions/phandle-array
196    description: |
197      Phandle to aspeed,ast2500-scu compatible syscon alongside register
198      offset and bit number to identify how the SIRQ polarity should be
199      configured. One possible data source is the LPC/eSPI mode bit. Only
200      applicable to aspeed,ast2500-vuart.
201    deprecated: true
202
203  aspeed,lpc-io-reg:
204    $ref: '/schemas/types.yaml#/definitions/uint32'
205    description: |
206      The VUART LPC address.  Only applicable to aspeed,ast2500-vuart.
207
208  aspeed,lpc-interrupts:
209    $ref: "/schemas/types.yaml#/definitions/uint32-array"
210    minItems: 2
211    maxItems: 2
212    description: |
213      A 2-cell property describing the VUART SIRQ number and SIRQ
214      polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH).  Only
215      applicable to aspeed,ast2500-vuart.
216
217required:
218  - reg
219  - interrupts
220
221unevaluatedProperties: false
222
223examples:
224  - |
225    serial@80230000 {
226        compatible = "ns8250";
227        reg = <0x80230000 0x100>;
228        interrupts = <10>;
229        reg-shift = <2>;
230        clock-frequency = <48000000>;
231    };
232  - |
233    #include <dt-bindings/gpio/gpio.h>
234    serial@49042000 {
235        compatible = "andestech,uart16550", "ns16550a";
236        reg = <0x49042000 0x400>;
237        interrupts = <80>;
238        clock-frequency = <48000000>;
239        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
240        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
241        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
242        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
243        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
244        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
245    };
246  - |
247    #include <dt-bindings/clock/aspeed-clock.h>
248    #include <dt-bindings/interrupt-controller/irq.h>
249    serial@1e787000 {
250        compatible = "aspeed,ast2500-vuart";
251        reg = <0x1e787000 0x40>;
252        reg-shift = <2>;
253        interrupts = <8>;
254        clocks = <&syscon ASPEED_CLK_APB>;
255        no-loopback-test;
256        aspeed,lpc-io-reg = <0x3f8>;
257        aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
258    };
259
260...
261