xref: /linux/Documentation/devicetree/bindings/serial/8250.yaml (revision 5f5598d945e2a69f764aa5c2074dad73e23bcfcb) 
1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter)
8
9maintainers:
10  - devicetree@vger.kernel.org
11
12allOf:
13  - $ref: serial.yaml#
14  - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15  - if:
16      anyOf:
17        - required:
18            - aspeed,lpc-io-reg
19        - required:
20            - aspeed,lpc-interrupts
21        - required:
22            - aspeed,sirq-polarity-sense
23    then:
24      properties:
25        compatible:
26          const: aspeed,ast2500-vuart
27  - if:
28      properties:
29        compatible:
30          const: mrvl,mmp-uart
31    then:
32      properties:
33        reg-shift:
34          const: 2
35      required:
36        - reg-shift
37  - if:
38      not:
39        properties:
40          compatible:
41            items:
42              - enum:
43                  - ns8250
44                  - ns16450
45                  - ns16550
46                  - ns16550a
47    then:
48      oneOf:
49        - required: [ clock-frequency ]
50        - required: [ clocks ]
51
52  - if:
53      properties:
54        compatible:
55          contains:
56            const: nxp,lpc1850-uart
57    then:
58      properties:
59        clock-names:
60          items:
61            - const: uartclk
62            - const: reg
63    else:
64      properties:
65        clock-names:
66          items:
67            - const: core
68            - const: bus
69
70properties:
71  compatible:
72    oneOf:
73      - const: ns8250
74      - const: ns16450
75      - const: ns16550
76      - const: ns16550a
77      - const: ns16850
78      - const: aspeed,ast2400-vuart
79      - const: aspeed,ast2500-vuart
80      - const: intel,xscale-uart
81      - const: mrvl,pxa-uart
82      - const: nuvoton,wpcm450-uart
83      - const: nuvoton,npcm750-uart
84      - const: nvidia,tegra20-uart
85      - const: nxp,lpc3220-uart
86      - items:
87          - enum:
88              - exar,xr16l2552
89              - exar,xr16l2551
90              - exar,xr16l2550
91          - const: ns8250
92      - items:
93          - enum:
94              - altr,16550-FIFO32
95              - altr,16550-FIFO64
96              - altr,16550-FIFO128
97              - fsl,16550-FIFO64
98              - andestech,uart16550
99              - nxp,lpc1850-uart
100              - opencores,uart16550-rtlsvn105
101              - ti,da830-uart
102          - const: ns16550a
103      - items:
104          - enum:
105              - ns16750
106              - fsl,ns16550
107              - cavium,octeon-3860-uart
108              - xlnx,xps-uart16550-2.00.b
109              - ralink,rt2880-uart
110          - enum:
111              - ns16550 # Deprecated, unless the FIFO really is broken
112              - ns16550a
113      - items:
114          - enum:
115              - nuvoton,npcm845-uart
116          - const: nuvoton,npcm750-uart
117      - items:
118          - enum:
119              - ralink,mt7620a-uart
120              - ralink,rt3052-uart
121              - ralink,rt3883-uart
122          - const: ralink,rt2880-uart
123          - enum:
124              - ns16550 # Deprecated, unless the FIFO really is broken
125              - ns16550a
126      - items:
127          - enum:
128              - mediatek,mt7622-btif
129              - mediatek,mt7623-btif
130          - const: mediatek,mtk-btif
131      - items:
132          - enum:
133              - mrvl,mmp-uart
134              - spacemit,k1-uart
135          - const: intel,xscale-uart
136      - items:
137          - enum:
138              - nvidia,tegra30-uart
139              - nvidia,tegra114-uart
140              - nvidia,tegra124-uart
141              - nvidia,tegra210-uart
142              - nvidia,tegra186-uart
143              - nvidia,tegra194-uart
144              - nvidia,tegra234-uart
145          - const: nvidia,tegra20-uart
146
147  reg:
148    maxItems: 1
149
150  interrupts:
151    maxItems: 1
152
153  clock-frequency: true
154
155  clocks:
156    minItems: 1
157    items:
158      - description: The core function clock
159      - description: An optional bus clock
160
161  clock-names:
162    minItems: 1
163    maxItems: 2
164    oneOf:
165      - items:
166          - const: core
167          - const: bus
168      - items:
169          - const: uartclk
170          - const: reg
171
172  dmas:
173    minItems: 1
174    maxItems: 4
175
176  dma-names:
177    minItems: 1
178    maxItems: 4
179
180  resets:
181    maxItems: 1
182
183  current-speed:
184    $ref: /schemas/types.yaml#/definitions/uint32
185    description: The current active speed of the UART.
186
187  reg-offset:
188    $ref: /schemas/types.yaml#/definitions/uint32
189    description: |
190      Offset to apply to the mapbase from the start of the registers.
191
192  reg-shift:
193    description: Quantity to shift the register offsets by.
194
195  reg-io-width:
196    description: |
197      The size (in bytes) of the IO accesses that should be performed on the
198      device. There are some systems that require 32-bit accesses to the
199      UART (e.g. TI davinci).
200
201  used-by-rtas:
202    type: boolean
203    description: |
204      Set to indicate that the port is in use by the OpenFirmware RTAS and
205      should not be registered.
206
207  no-loopback-test:
208    type: boolean
209    description: |
210      Set to indicate that the port does not implement loopback test mode.
211
212  fifo-size:
213    $ref: /schemas/types.yaml#/definitions/uint32
214    description: The fifo size of the UART.
215
216  auto-flow-control:
217    type: boolean
218    description: |
219      One way to enable automatic flow control support. The driver is
220      allowed to detect support for the capability even without this
221      property.
222
223  tx-threshold:
224    description: |
225      Specify the TX FIFO low water indication for parts with programmable
226      TX FIFO thresholds.
227
228  overrun-throttle-ms:
229    description: |
230      How long to pause uart rx when input overrun is encountered.
231
232  rts-gpios: true
233  cts-gpios: true
234  dtr-gpios: true
235  dsr-gpios: true
236  rng-gpios: true
237  dcd-gpios: true
238
239  aspeed,sirq-polarity-sense:
240    $ref: /schemas/types.yaml#/definitions/phandle-array
241    description: |
242      Phandle to aspeed,ast2500-scu compatible syscon alongside register
243      offset and bit number to identify how the SIRQ polarity should be
244      configured. One possible data source is the LPC/eSPI mode bit. Only
245      applicable to aspeed,ast2500-vuart.
246    deprecated: true
247
248  aspeed,lpc-io-reg:
249    $ref: /schemas/types.yaml#/definitions/uint32-array
250    maxItems: 1
251    description: |
252      The VUART LPC address.  Only applicable to aspeed,ast2500-vuart.
253
254  aspeed,lpc-interrupts:
255    $ref: /schemas/types.yaml#/definitions/uint32-array
256    minItems: 2
257    maxItems: 2
258    description: |
259      A 2-cell property describing the VUART SIRQ number and SIRQ
260      polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH).  Only
261      applicable to aspeed,ast2500-vuart.
262
263required:
264  - reg
265  - interrupts
266
267if:
268  properties:
269    compatible:
270      contains:
271        enum:
272          - spacemit,k1-uart
273          - nxp,lpc1850-uart
274then:
275  required:
276    - clocks
277    - clock-names
278  properties:
279    clocks:
280      minItems: 2
281    clock-names:
282      minItems: 2
283else:
284  properties:
285    clocks:
286      maxItems: 1
287    clock-names:
288      maxItems: 1
289
290unevaluatedProperties: false
291
292examples:
293  - |
294    serial@80230000 {
295        compatible = "ns8250";
296        reg = <0x80230000 0x100>;
297        interrupts = <10>;
298        reg-shift = <2>;
299        clock-frequency = <48000000>;
300    };
301  - |
302    #include <dt-bindings/gpio/gpio.h>
303    serial@49042000 {
304        compatible = "andestech,uart16550", "ns16550a";
305        reg = <0x49042000 0x400>;
306        interrupts = <80>;
307        clock-frequency = <48000000>;
308        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
309        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
310        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
311        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
312        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
313        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
314    };
315  - |
316    #include <dt-bindings/clock/aspeed-clock.h>
317    #include <dt-bindings/interrupt-controller/irq.h>
318    serial@1e787000 {
319        compatible = "aspeed,ast2500-vuart";
320        reg = <0x1e787000 0x40>;
321        reg-shift = <2>;
322        interrupts = <8>;
323        clocks = <&syscon ASPEED_CLK_APB>;
324        no-loopback-test;
325        aspeed,lpc-io-reg = <0x3f8>;
326        aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
327    };
328
329...
330