1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk> 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/serial/8250.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: UART (Universal Asynchronous Receiver/Transmitter) 8 9maintainers: 10 - devicetree@vger.kernel.org 11 12allOf: 13 - $ref: serial.yaml# 14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# 15 - if: 16 anyOf: 17 - required: 18 - aspeed,lpc-io-reg 19 - required: 20 - aspeed,lpc-interrupts 21 - required: 22 - aspeed,sirq-polarity-sense 23 then: 24 properties: 25 compatible: 26 const: aspeed,ast2500-vuart 27 - if: 28 properties: 29 compatible: 30 const: mrvl,mmp-uart 31 then: 32 properties: 33 reg-shift: 34 const: 2 35 required: 36 - reg-shift 37 - if: 38 not: 39 properties: 40 compatible: 41 items: 42 - enum: 43 - ns8250 44 - ns16450 45 - ns16550 46 - ns16550a 47 then: 48 oneOf: 49 - required: [ clock-frequency ] 50 - required: [ clocks ] 51 - if: 52 properties: 53 compatible: 54 contains: 55 const: nxp,lpc1850-uart 56 then: 57 properties: 58 clock-names: 59 items: 60 - const: uartclk 61 - const: reg 62 - if: 63 properties: 64 compatible: 65 contains: 66 enum: 67 - spacemit,k1-uart 68 - spacemit,k3-uart 69 then: 70 properties: 71 clock-names: 72 items: 73 - const: core 74 - const: bus 75 - if: 76 properties: 77 compatible: 78 contains: 79 enum: 80 - spacemit,k1-uart 81 - spacemit,k3-uart 82 - nxp,lpc1850-uart 83 then: 84 required: 85 - clocks 86 - clock-names 87 properties: 88 clocks: 89 minItems: 2 90 clock-names: 91 minItems: 2 92 else: 93 properties: 94 clocks: 95 maxItems: 1 96 clock-names: 97 maxItems: 1 98 99properties: 100 compatible: 101 oneOf: 102 - const: ns8250 103 - const: ns16450 104 - const: ns16550 105 - const: ns16550a 106 - const: ns16850 107 - const: aspeed,ast2400-vuart 108 - const: aspeed,ast2500-vuart 109 - const: intel,xscale-uart 110 - const: mrvl,pxa-uart 111 - const: nuvoton,wpcm450-uart 112 - const: nuvoton,npcm750-uart 113 - const: nvidia,tegra20-uart 114 - const: nxp,lpc3220-uart 115 - items: 116 - enum: 117 - exar,xr16l2552 118 - exar,xr16l2551 119 - exar,xr16l2550 120 - const: ns8250 121 - items: 122 - enum: 123 - altr,16550-FIFO32 124 - altr,16550-FIFO64 125 - altr,16550-FIFO128 126 - fsl,16550-FIFO64 127 - andestech,uart16550 128 - nxp,lpc1850-uart 129 - opencores,uart16550-rtlsvn105 130 - ti,da830-uart 131 - loongson,ls2k0500-uart 132 - loongson,ls2k1500-uart 133 - const: ns16550a 134 - items: 135 - enum: 136 - ns16750 137 - fsl,ns16550 138 - cavium,octeon-3860-uart 139 - xlnx,xps-uart16550-2.00.b 140 - ralink,rt2880-uart 141 - enum: 142 - ns16550 # Deprecated, unless the FIFO really is broken 143 - ns16550a 144 - items: 145 - enum: 146 - nuvoton,npcm845-uart 147 - const: nuvoton,npcm750-uart 148 - items: 149 - enum: 150 - ralink,mt7620a-uart 151 - ralink,rt3052-uart 152 - ralink,rt3883-uart 153 - const: ralink,rt2880-uart 154 - enum: 155 - ns16550 # Deprecated, unless the FIFO really is broken 156 - ns16550a 157 - items: 158 - enum: 159 - mediatek,mt7622-btif 160 - mediatek,mt7623-btif 161 - const: mediatek,mtk-btif 162 - items: 163 - enum: 164 - mrvl,mmp-uart 165 - spacemit,k1-uart 166 - spacemit,k3-uart 167 - const: intel,xscale-uart 168 - items: 169 - enum: 170 - nvidia,tegra30-uart 171 - nvidia,tegra114-uart 172 - nvidia,tegra124-uart 173 - nvidia,tegra210-uart 174 - nvidia,tegra186-uart 175 - nvidia,tegra194-uart 176 - nvidia,tegra234-uart 177 - const: nvidia,tegra20-uart 178 - items: 179 - enum: 180 - loongson,ls2k1000-uart 181 - const: loongson,ls2k0500-uart 182 - const: ns16550a 183 - items: 184 - enum: 185 - loongson,ls3a4000-uart 186 - loongson,ls3a5000-uart 187 - loongson,ls3a6000-uart 188 - loongson,ls2k2000-uart 189 - const: loongson,ls2k1500-uart 190 - const: ns16550a 191 192 reg: 193 maxItems: 1 194 195 interrupts: 196 maxItems: 1 197 198 clock-frequency: true 199 200 clocks: 201 minItems: 1 202 items: 203 - description: The core function clock 204 - description: An optional bus clock 205 206 clock-names: 207 minItems: 1 208 maxItems: 2 209 oneOf: 210 - enum: 211 - main 212 - uart 213 - items: 214 - const: core 215 - const: bus 216 - items: 217 - const: uartclk 218 - const: reg 219 220 dmas: 221 minItems: 1 222 maxItems: 4 223 224 dma-names: 225 minItems: 1 226 maxItems: 4 227 228 resets: 229 maxItems: 1 230 231 current-speed: 232 $ref: /schemas/types.yaml#/definitions/uint32 233 description: The current active speed of the UART. 234 235 reg-offset: 236 $ref: /schemas/types.yaml#/definitions/uint32 237 description: | 238 Offset to apply to the mapbase from the start of the registers. 239 240 reg-shift: 241 description: Quantity to shift the register offsets by. 242 243 reg-io-width: 244 description: | 245 The size (in bytes) of the IO accesses that should be performed on the 246 device. There are some systems that require 32-bit accesses to the 247 UART (e.g. TI davinci). 248 249 used-by-rtas: 250 type: boolean 251 description: | 252 Set to indicate that the port is in use by the OpenFirmware RTAS and 253 should not be registered. 254 255 no-loopback-test: 256 type: boolean 257 description: | 258 Set to indicate that the port does not implement loopback test mode. 259 260 fifo-size: 261 $ref: /schemas/types.yaml#/definitions/uint32 262 description: The fifo size of the UART. 263 264 auto-flow-control: 265 type: boolean 266 description: | 267 One way to enable automatic flow control support. The driver is 268 allowed to detect support for the capability even without this 269 property. 270 271 tx-threshold: 272 description: | 273 Specify the TX FIFO low water indication for parts with programmable 274 TX FIFO thresholds. 275 276 overrun-throttle-ms: 277 description: | 278 How long to pause uart rx when input overrun is encountered. 279 280 rts-gpios: true 281 cts-gpios: true 282 dtr-gpios: true 283 dsr-gpios: true 284 rng-gpios: true 285 dcd-gpios: true 286 287 aspeed,sirq-polarity-sense: 288 $ref: /schemas/types.yaml#/definitions/phandle-array 289 description: | 290 Phandle to aspeed,ast2500-scu compatible syscon alongside register 291 offset and bit number to identify how the SIRQ polarity should be 292 configured. One possible data source is the LPC/eSPI mode bit. Only 293 applicable to aspeed,ast2500-vuart. 294 deprecated: true 295 296 aspeed,lpc-io-reg: 297 $ref: /schemas/types.yaml#/definitions/uint32-array 298 maxItems: 1 299 description: | 300 The VUART LPC address. Only applicable to aspeed,ast2500-vuart. 301 302 aspeed,lpc-interrupts: 303 $ref: /schemas/types.yaml#/definitions/uint32-array 304 minItems: 2 305 maxItems: 2 306 description: | 307 A 2-cell property describing the VUART SIRQ number and SIRQ 308 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only 309 applicable to aspeed,ast2500-vuart. 310 311required: 312 - reg 313 - interrupts 314 315unevaluatedProperties: false 316 317examples: 318 - | 319 serial@80230000 { 320 compatible = "ns8250"; 321 reg = <0x80230000 0x100>; 322 interrupts = <10>; 323 reg-shift = <2>; 324 clock-frequency = <48000000>; 325 }; 326 - | 327 #include <dt-bindings/gpio/gpio.h> 328 serial@49042000 { 329 compatible = "andestech,uart16550", "ns16550a"; 330 reg = <0x49042000 0x400>; 331 interrupts = <80>; 332 clock-frequency = <48000000>; 333 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; 334 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; 335 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 336 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 337 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 338 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 339 }; 340 - | 341 #include <dt-bindings/clock/aspeed-clock.h> 342 #include <dt-bindings/interrupt-controller/irq.h> 343 serial@1e787000 { 344 compatible = "aspeed,ast2500-vuart"; 345 reg = <0x1e787000 0x40>; 346 reg-shift = <2>; 347 interrupts = <8>; 348 clocks = <&syscon ASPEED_CLK_APB>; 349 no-loopback-test; 350 aspeed,lpc-io-reg = <0x3f8>; 351 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 352 }; 353 354... 355