1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk> 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/serial/8250.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: UART (Universal Asynchronous Receiver/Transmitter) 8 9maintainers: 10 - devicetree@vger.kernel.org 11 12allOf: 13 - $ref: serial.yaml# 14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# 15 - if: 16 anyOf: 17 - required: 18 - aspeed,lpc-io-reg 19 - required: 20 - aspeed,lpc-interrupts 21 - required: 22 - aspeed,sirq-polarity-sense 23 then: 24 properties: 25 compatible: 26 contains: 27 const: aspeed,ast2500-vuart 28 - if: 29 properties: 30 compatible: 31 const: mrvl,mmp-uart 32 then: 33 properties: 34 reg-shift: 35 const: 2 36 required: 37 - reg-shift 38 - if: 39 not: 40 properties: 41 compatible: 42 items: 43 - enum: 44 - ns8250 45 - ns16450 46 - ns16550 47 - ns16550a 48 then: 49 oneOf: 50 - required: [ clock-frequency ] 51 - required: [ clocks ] 52 - if: 53 properties: 54 compatible: 55 contains: 56 const: nxp,lpc1850-uart 57 then: 58 properties: 59 clock-names: 60 items: 61 - const: uartclk 62 - const: reg 63 - if: 64 properties: 65 compatible: 66 contains: 67 enum: 68 - spacemit,k1-uart 69 - spacemit,k3-uart 70 then: 71 properties: 72 clock-names: 73 items: 74 - const: core 75 - const: bus 76 - if: 77 properties: 78 compatible: 79 contains: 80 enum: 81 - spacemit,k1-uart 82 - spacemit,k3-uart 83 - nxp,lpc1850-uart 84 then: 85 required: 86 - clocks 87 - clock-names 88 properties: 89 clocks: 90 minItems: 2 91 clock-names: 92 minItems: 2 93 else: 94 properties: 95 clocks: 96 maxItems: 1 97 clock-names: 98 maxItems: 1 99 100properties: 101 compatible: 102 oneOf: 103 - const: ns8250 104 - const: ns16450 105 - const: ns16550 106 - const: ns16550a 107 - const: ns16850 108 - const: aspeed,ast2400-vuart 109 - const: aspeed,ast2500-vuart 110 - const: intel,xscale-uart 111 - const: mrvl,pxa-uart 112 - const: nuvoton,wpcm450-uart 113 - const: nuvoton,npcm750-uart 114 - const: nvidia,tegra20-uart 115 - const: nxp,lpc3220-uart 116 - items: 117 - enum: 118 - exar,xr16l2552 119 - exar,xr16l2551 120 - exar,xr16l2550 121 - const: ns8250 122 - items: 123 - enum: 124 - altr,16550-FIFO32 125 - altr,16550-FIFO64 126 - altr,16550-FIFO128 127 - fsl,16550-FIFO64 128 - andestech,uart16550 129 - nxp,lpc1850-uart 130 - opencores,uart16550-rtlsvn105 131 - ti,da830-uart 132 - loongson,ls2k0500-uart 133 - loongson,ls2k1500-uart 134 - const: ns16550a 135 - items: 136 - enum: 137 - ns16750 138 - fsl,ns16550 139 - cavium,octeon-3860-uart 140 - xlnx,xps-uart16550-2.00.b 141 - ralink,rt2880-uart 142 - enum: 143 - ns16550 # Deprecated, unless the FIFO really is broken 144 - ns16550a 145 - items: 146 - enum: 147 - nuvoton,npcm845-uart 148 - const: nuvoton,npcm750-uart 149 - items: 150 - enum: 151 - ralink,mt7620a-uart 152 - ralink,rt3052-uart 153 - ralink,rt3883-uart 154 - const: ralink,rt2880-uart 155 - enum: 156 - ns16550 # Deprecated, unless the FIFO really is broken 157 - ns16550a 158 - items: 159 - enum: 160 - mediatek,mt7622-btif 161 - mediatek,mt7623-btif 162 - const: mediatek,mtk-btif 163 - items: 164 - enum: 165 - mrvl,mmp-uart 166 - spacemit,k1-uart 167 - spacemit,k3-uart 168 - const: intel,xscale-uart 169 - items: 170 - enum: 171 - nvidia,tegra30-uart 172 - nvidia,tegra114-uart 173 - nvidia,tegra124-uart 174 - nvidia,tegra210-uart 175 - nvidia,tegra186-uart 176 - nvidia,tegra194-uart 177 - nvidia,tegra234-uart 178 - const: nvidia,tegra20-uart 179 - items: 180 - enum: 181 - loongson,ls2k1000-uart 182 - const: loongson,ls2k0500-uart 183 - const: ns16550a 184 - items: 185 - enum: 186 - loongson,ls3a4000-uart 187 - loongson,ls3a5000-uart 188 - loongson,ls3a6000-uart 189 - loongson,ls2k2000-uart 190 - const: loongson,ls2k1500-uart 191 - const: ns16550a 192 - items: 193 - enum: 194 - aspeed,ast2600-vuart 195 - aspeed,ast2700-vuart 196 - const: aspeed,ast2500-vuart 197 198 reg: 199 maxItems: 1 200 201 interrupts: 202 maxItems: 1 203 204 clock-frequency: true 205 206 clocks: 207 minItems: 1 208 items: 209 - description: The core function clock 210 - description: An optional bus clock 211 212 clock-names: 213 minItems: 1 214 maxItems: 2 215 oneOf: 216 - enum: 217 - main 218 - uart 219 - items: 220 - const: core 221 - const: bus 222 - items: 223 - const: uartclk 224 - const: reg 225 226 dmas: 227 minItems: 1 228 maxItems: 4 229 230 dma-names: 231 minItems: 1 232 maxItems: 4 233 234 resets: 235 maxItems: 1 236 237 current-speed: 238 $ref: /schemas/types.yaml#/definitions/uint32 239 description: The current active speed of the UART. 240 241 reg-offset: 242 $ref: /schemas/types.yaml#/definitions/uint32 243 description: | 244 Offset to apply to the mapbase from the start of the registers. 245 246 reg-shift: 247 description: Quantity to shift the register offsets by. 248 249 reg-io-width: 250 description: | 251 The size (in bytes) of the IO accesses that should be performed on the 252 device. There are some systems that require 32-bit accesses to the 253 UART (e.g. TI davinci). 254 255 used-by-rtas: 256 type: boolean 257 description: | 258 Set to indicate that the port is in use by the OpenFirmware RTAS and 259 should not be registered. 260 261 no-loopback-test: 262 type: boolean 263 description: | 264 Set to indicate that the port does not implement loopback test mode. 265 266 fifo-size: 267 $ref: /schemas/types.yaml#/definitions/uint32 268 description: The fifo size of the UART. 269 270 auto-flow-control: 271 type: boolean 272 description: | 273 One way to enable automatic flow control support. The driver is 274 allowed to detect support for the capability even without this 275 property. 276 277 tx-threshold: 278 description: | 279 Specify the TX FIFO low water indication for parts with programmable 280 TX FIFO thresholds. 281 282 overrun-throttle-ms: 283 description: | 284 How long to pause uart rx when input overrun is encountered. 285 286 rts-gpios: true 287 cts-gpios: true 288 dtr-gpios: true 289 dsr-gpios: true 290 rng-gpios: true 291 dcd-gpios: true 292 293 aspeed,sirq-polarity-sense: 294 $ref: /schemas/types.yaml#/definitions/phandle-array 295 description: | 296 Phandle to aspeed,ast2500-scu compatible syscon alongside register 297 offset and bit number to identify how the SIRQ polarity should be 298 configured. One possible data source is the LPC/eSPI mode bit. Only 299 applicable to aspeed,ast2500-vuart. 300 deprecated: true 301 302 aspeed,lpc-io-reg: 303 $ref: /schemas/types.yaml#/definitions/uint32-array 304 maxItems: 1 305 description: | 306 The VUART LPC address. Only applicable to aspeed,ast2500-vuart. 307 308 aspeed,lpc-interrupts: 309 $ref: /schemas/types.yaml#/definitions/uint32-array 310 minItems: 2 311 maxItems: 2 312 description: | 313 A 2-cell property describing the VUART SIRQ number and SIRQ 314 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only 315 applicable to aspeed,ast2500-vuart. 316 317required: 318 - reg 319 - interrupts 320 321unevaluatedProperties: false 322 323examples: 324 - | 325 serial@80230000 { 326 compatible = "ns8250"; 327 reg = <0x80230000 0x100>; 328 interrupts = <10>; 329 reg-shift = <2>; 330 clock-frequency = <48000000>; 331 }; 332 - | 333 #include <dt-bindings/gpio/gpio.h> 334 serial@49042000 { 335 compatible = "andestech,uart16550", "ns16550a"; 336 reg = <0x49042000 0x400>; 337 interrupts = <80>; 338 clock-frequency = <48000000>; 339 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; 340 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; 341 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 342 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 343 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 344 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 345 }; 346 - | 347 #include <dt-bindings/clock/aspeed-clock.h> 348 #include <dt-bindings/interrupt-controller/irq.h> 349 serial@1e787000 { 350 compatible = "aspeed,ast2500-vuart"; 351 reg = <0x1e787000 0x40>; 352 reg-shift = <2>; 353 interrupts = <8>; 354 clocks = <&syscon ASPEED_CLK_APB>; 355 no-loopback-test; 356 aspeed,lpc-io-reg = <0x3f8>; 357 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 358 }; 359 360... 361