1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/rtc/nxp,s32g-rtc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP S32G2/S32G3 Real Time Clock (RTC) 8 9maintainers: 10 - Bogdan Hamciuc <bogdan.hamciuc@nxp.com> 11 - Ciprian Marian Costea <ciprianmarian.costea@nxp.com> 12 13description: 14 RTC hardware module present on S32G2/S32G3 SoCs is used as a wakeup source. 15 It is not kept alive during system reset and it is not battery-powered. 16 17allOf: 18 - $ref: rtc.yaml# 19 20properties: 21 compatible: 22 oneOf: 23 - enum: 24 - nxp,s32g2-rtc 25 - items: 26 - const: nxp,s32g3-rtc 27 - const: nxp,s32g2-rtc 28 29 reg: 30 maxItems: 1 31 32 interrupts: 33 maxItems: 1 34 35 clocks: 36 items: 37 - description: ipg clock drives the access to the RTC iomapped registers 38 - description: Clock source for the RTC module. Can be selected between 39 4 different clock sources using an integrated hardware mux. 40 On S32G2/S32G3 SoCs, 'source0' is the SIRC clock (~32KHz) and it is 41 available during standby and runtime. 'source1' is reserved and cannot 42 be used. 'source2' is the FIRC clock and it is only available during 43 runtime providing a better resolution (~48MHz). 'source3' is an external 44 RTC clock source which can be additionally added in hardware. 45 46 clock-names: 47 items: 48 - const: ipg 49 - enum: [ source0, source1, source2, source3 ] 50 51required: 52 - compatible 53 - reg 54 - interrupts 55 - clocks 56 - clock-names 57 58additionalProperties: false 59 60examples: 61 - | 62 #include <dt-bindings/interrupt-controller/arm-gic.h> 63 #include <dt-bindings/interrupt-controller/irq.h> 64 65 rtc@40060000 { 66 compatible = "nxp,s32g3-rtc", 67 "nxp,s32g2-rtc"; 68 reg = <0x40060000 0x1000>; 69 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 70 clocks = <&clks 54>, <&clks 55>; 71 clock-names = "ipg", "source0"; 72 }; 73