xref: /linux/Documentation/devicetree/bindings/rtc/atmel,at91sam9260-rtt.yaml (revision 0526b56cbc3c489642bd6a5fe4b718dea7ef0ee8) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/rtc/atmel,at91sam9260-rtt.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Atmel AT91 RTT
9
10allOf:
11  - $ref: rtc.yaml#
12
13maintainers:
14  - Alexandre Belloni <alexandre.belloni@bootlin.com>
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - const: atmel,at91sam9260-rtt
21      - items:
22          - const: microchip,sam9x60-rtt
23          - const: atmel,at91sam9260-rtt
24      - items:
25          - const: microchip,sama7g5-rtt
26          - const: microchip,sam9x60-rtt
27          - const: atmel,at91sam9260-rtt
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35  clocks:
36    maxItems: 1
37
38  atmel,rtt-rtc-time-reg:
39    $ref: /schemas/types.yaml#/definitions/phandle-array
40    items:
41      - items:
42          - description: Phandle to the GPBR node.
43          - description: Offset within the GPBR block.
44    description:
45      Should encode the GPBR register used to store the time base when the
46      RTT is used as an RTC. The first cell should point to the GPBR node
47      and the second one encodes the offset within the GPBR block (or in
48      other words, the GPBR register used to store the time base).
49
50required:
51  - compatible
52  - reg
53  - interrupts
54  - clocks
55  - atmel,rtt-rtc-time-reg
56
57unevaluatedProperties: false
58
59examples:
60  - |
61    #include <dt-bindings/interrupt-controller/irq.h>
62
63    rtc@fffffd20 {
64        compatible = "atmel,at91sam9260-rtt";
65        reg = <0xfffffd20 0x10>;
66        interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
67        clocks = <&clk32k>;
68        atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
69    };
70