xref: /linux/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml (revision 621cde16e49b3ecf7d59a8106a20aaebfb4a59a9)
15059791eSBenjamin Gaignard# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
25059791eSBenjamin Gaignard%YAML 1.2
35059791eSBenjamin Gaignard---
45059791eSBenjamin Gaignard$id: http://devicetree.org/schemas/rng/st,stm32-rng.yaml#
55059791eSBenjamin Gaignard$schema: http://devicetree.org/meta-schemas/core.yaml#
65059791eSBenjamin Gaignard
784e85359SKrzysztof Kozlowskititle: STMicroelectronics STM32 RNG
85059791eSBenjamin Gaignard
95059791eSBenjamin Gaignarddescription: |
105059791eSBenjamin Gaignard  The STM32 hardware random number generator is a simple fixed purpose
115059791eSBenjamin Gaignard  IP and is fully separated from other crypto functions.
125059791eSBenjamin Gaignard
135059791eSBenjamin Gaignardmaintainers:
14f4eedebdSPatrice Chotard  - Lionel Debieve <lionel.debieve@foss.st.com>
155059791eSBenjamin Gaignard
165059791eSBenjamin Gaignardproperties:
175059791eSBenjamin Gaignard  compatible:
180d2d67b4SGatien Chevallier    enum:
190d2d67b4SGatien Chevallier      - st,stm32-rng
200d2d67b4SGatien Chevallier      - st,stm32mp13-rng
215059791eSBenjamin Gaignard
225059791eSBenjamin Gaignard  reg:
235059791eSBenjamin Gaignard    maxItems: 1
245059791eSBenjamin Gaignard
255059791eSBenjamin Gaignard  clocks:
265059791eSBenjamin Gaignard    maxItems: 1
275059791eSBenjamin Gaignard
285059791eSBenjamin Gaignard  resets:
295059791eSBenjamin Gaignard    maxItems: 1
305059791eSBenjamin Gaignard
315059791eSBenjamin Gaignard  clock-error-detect:
324e71ed98SRob Herring    type: boolean
335059791eSBenjamin Gaignard    description: If set enable the clock detection management
345059791eSBenjamin Gaignard
350d2d67b4SGatien Chevallier  st,rng-lock-conf:
360d2d67b4SGatien Chevallier    type: boolean
370d2d67b4SGatien Chevallier    description: If set, the RNG configuration in RNG_CR, RNG_HTCR and
380d2d67b4SGatien Chevallier                  RNG_NSCR will be locked.
390d2d67b4SGatien Chevallier
40*02ec75edSGatien Chevallier  access-controllers:
41*02ec75edSGatien Chevallier    minItems: 1
42*02ec75edSGatien Chevallier    maxItems: 2
43*02ec75edSGatien Chevallier
445059791eSBenjamin Gaignardrequired:
455059791eSBenjamin Gaignard  - compatible
465059791eSBenjamin Gaignard  - reg
475059791eSBenjamin Gaignard  - clocks
485059791eSBenjamin Gaignard
490d2d67b4SGatien ChevallierallOf:
500d2d67b4SGatien Chevallier  - if:
510d2d67b4SGatien Chevallier      properties:
520d2d67b4SGatien Chevallier        compatible:
530d2d67b4SGatien Chevallier          contains:
540d2d67b4SGatien Chevallier            enum:
550d2d67b4SGatien Chevallier              - st,stm32-rng
560d2d67b4SGatien Chevallier    then:
570d2d67b4SGatien Chevallier      properties:
580d2d67b4SGatien Chevallier        st,rng-lock-conf: false
590d2d67b4SGatien Chevallier
605059791eSBenjamin GaignardadditionalProperties: false
615059791eSBenjamin Gaignard
625059791eSBenjamin Gaignardexamples:
635059791eSBenjamin Gaignard  - |
645059791eSBenjamin Gaignard    #include <dt-bindings/clock/stm32mp1-clks.h>
655059791eSBenjamin Gaignard    rng@54003000 {
665059791eSBenjamin Gaignard      compatible = "st,stm32-rng";
675059791eSBenjamin Gaignard      reg = <0x54003000 0x400>;
685059791eSBenjamin Gaignard      clocks = <&rcc RNG1_K>;
695059791eSBenjamin Gaignard    };
705059791eSBenjamin Gaignard
715059791eSBenjamin Gaignard...
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