1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27select: 28 properties: 29 compatible: 30 contains: 31 const: riscv 32 33properties: 34 riscv,isa: 35 description: 36 Identifies the specific RISC-V instruction set architecture 37 supported by the hart. These are documented in the RISC-V 38 User-Level ISA document, available from 39 https://riscv.org/specifications/ 40 41 Due to revisions of the ISA specification, some deviations 42 have arisen over time. 43 Notably, riscv,isa was defined prior to the creation of the 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45 implies "zicntr_zicsr_zifencei_zihpm". 46 47 While the isa strings in ISA specification are case 48 insensitive, letters in the riscv,isa string must be all 49 lowercase. 50 $ref: /schemas/types.yaml#/definitions/string 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 52 deprecated: true 53 54 riscv,isa-base: 55 description: 56 The base ISA implemented by this hart, as described by the 20191213 57 version of the unprivileged ISA specification. 58 enum: 59 - rv32i 60 - rv64i 61 62 riscv,isa-extensions: 63 $ref: /schemas/types.yaml#/definitions/string-array 64 minItems: 1 65 description: Extensions supported by the hart. 66 items: 67 anyOf: 68 # single letter extensions, in canonical order 69 - const: i 70 description: | 71 The base integer instruction set, as ratified in the 20191213 72 version of the unprivileged ISA specification. 73 74 This does not include Chapter 10, "Counters", which was moved into 75 the Zicntr and Zihpm extensions after the ratification of the 76 20191213 version of the unprivileged specification. 77 78 - const: m 79 description: 80 The standard M extension for integer multiplication and division, as 81 ratified in the 20191213 version of the unprivileged ISA 82 specification. 83 84 - const: a 85 description: 86 The standard A extension for atomic instructions, as ratified in the 87 20191213 version of the unprivileged ISA specification. 88 89 - const: f 90 description: 91 The standard F extension for single-precision floating point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: d 96 description: 97 The standard D extension for double-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: q 102 description: 103 The standard Q extension for quad-precision floating-point, as 104 ratified in the 20191213 version of the unprivileged ISA 105 specification. 106 107 - const: c 108 description: 109 The standard C extension for compressed instructions, as ratified in 110 the 20191213 version of the unprivileged ISA specification. 111 112 - const: v 113 description: 114 The standard V extension for vector operations, as ratified 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116 encoding") of the riscv-v-spec. 117 118 - const: h 119 description: 120 The standard H extension for hypervisors as ratified in the 20191213 121 version of the privileged ISA specification. 122 123 # multi-letter extensions, sorted alphanumerically 124 - const: smaia 125 description: | 126 The standard Smaia supervisor-level extension for the advanced 127 interrupt architecture for machine-mode-visible csr and behavioural 128 changes to interrupts as frozen at commit ccbddab ("Merge pull 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130 131 - const: smmpm 132 description: | 133 The standard Smmpm extension for M-mode pointer masking as 134 ratified at commit d70011dde6c2 ("Update to ratified state") 135 of riscv-j-extension. 136 137 - const: smnpm 138 description: | 139 The standard Smnpm extension for next-mode pointer masking as 140 ratified at commit d70011dde6c2 ("Update to ratified state") 141 of riscv-j-extension. 142 143 - const: smstateen 144 description: | 145 The standard Smstateen extension for controlling access to CSRs 146 added by other RISC-V extensions in H/S/VS/U/VU modes and as 147 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 148 149 - const: ssaia 150 description: | 151 The standard Ssaia supervisor-level extension for the advanced 152 interrupt architecture for supervisor-mode-visible csr and 153 behavioural changes to interrupts as frozen at commit ccbddab 154 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 155 156 - const: sscofpmf 157 description: | 158 The standard Sscofpmf supervisor-level extension for count overflow 159 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 160 to manually trigger workflow. (#2)") of riscv-count-overflow. 161 162 - const: ssnpm 163 description: | 164 The standard Ssnpm extension for next-mode pointer masking as 165 ratified at commit d70011dde6c2 ("Update to ratified state") 166 of riscv-j-extension. 167 168 - const: sstc 169 description: | 170 The standard Sstc supervisor-level extension for time compare as 171 ratified at commit 3f9ed34 ("Add ability to manually trigger 172 workflow. (#2)") of riscv-time-compare. 173 174 - const: svade 175 description: | 176 The standard Svade supervisor-level extension for SW-managed PTE A/D 177 bit updates as ratified in the 20240213 version of the privileged 178 ISA specification. 179 180 Both Svade and Svadu extensions control the hardware behavior when 181 the PTE A/D bits need to be set. The default behavior for the four 182 possible combinations of these extensions in the device tree are: 183 1) Neither Svade nor Svadu present in DT => It is technically 184 unknown whether the platform uses Svade or Svadu. Supervisor 185 software should be prepared to handle either hardware updating 186 of the PTE A/D bits or page faults when they need updated. 187 2) Only Svade present in DT => Supervisor must assume Svade to be 188 always enabled. 189 3) Only Svadu present in DT => Supervisor must assume Svadu to be 190 always enabled. 191 4) Both Svade and Svadu present in DT => Supervisor must assume 192 Svadu turned-off at boot time. To use Svadu, supervisor must 193 explicitly enable it using the SBI FWFT extension. 194 195 - const: svadu 196 description: | 197 The standard Svadu supervisor-level extension for hardware updating 198 of PTE A/D bits as ratified in the 20240528 version of the 199 privileged ISA specification. Please refer to Svade dt-binding 200 description for more details. 201 202 - const: svinval 203 description: 204 The standard Svinval supervisor-level extension for fine-grained 205 address-translation cache invalidation as ratified in the 20191213 206 version of the privileged ISA specification. 207 208 - const: svnapot 209 description: 210 The standard Svnapot supervisor-level extensions for napot 211 translation contiguity as ratified in the 20191213 version of the 212 privileged ISA specification. 213 214 - const: svpbmt 215 description: 216 The standard Svpbmt supervisor-level extensions for page-based 217 memory types as ratified in the 20191213 version of the privileged 218 ISA specification. 219 220 - const: svrsw60t59b 221 description: 222 The Svrsw60t59b extension for providing two more bits[60:59] to 223 PTE/PMD entry as ratified at commit 28bde925e7a7 ("PTE Reserved 224 for SW bits 60:59") of riscv-non-isa/riscv-iommu. 225 226 - const: svvptc 227 description: 228 The standard Svvptc supervisor-level extension for 229 address-translation cache behaviour with respect to invalid entries 230 as ratified at commit 4a69197e5617 ("Update to ratified state") of 231 riscv-svvptc. 232 233 - const: zaamo 234 description: | 235 The standard Zaamo extension for atomic memory operations as 236 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 237 (#1304)") of the unprivileged ISA specification. 238 239 - const: zabha 240 description: | 241 The Zabha extension for Byte and Halfword Atomic Memory Operations 242 as ratified at commit 49f49c842ff9 ("Update to Rafified state") of 243 riscv-zabha. 244 245 - const: zacas 246 description: | 247 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 248 is supported as ratified at commit 5059e0ca641c ("update to 249 ratified") of the riscv-zacas. 250 251 - const: zalasr 252 description: | 253 The standard Zalasr extension for load-acquire/store-release as frozen 254 at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. 255 256 - const: zalrsc 257 description: | 258 The standard Zalrsc extension for load-reserved/store-conditional as 259 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 260 (#1304)") of the unprivileged ISA specification. 261 262 - const: zawrs 263 description: | 264 The Zawrs extension for entering a low-power state or for trapping 265 to a hypervisor while waiting on a store to a memory location, as 266 ratified in commit 98918c844281 ("Merge pull request #1217 from 267 riscv/zawrs") of riscv-isa-manual. 268 269 - const: zba 270 description: | 271 The standard Zba bit-manipulation extension for address generation 272 acceleration instructions as ratified at commit 6d33919 ("Merge pull 273 request #158 from hirooih/clmul-fix-loop-end-condition") of 274 riscv-bitmanip. 275 276 - const: zbb 277 description: | 278 The standard Zbb bit-manipulation extension for basic bit-manipulation 279 as ratified at commit 6d33919 ("Merge pull request #158 from 280 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 281 282 - const: zbc 283 description: | 284 The standard Zbc bit-manipulation extension for carry-less 285 multiplication as ratified at commit 6d33919 ("Merge pull request 286 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 287 288 - const: zbkb 289 description: 290 The standard Zbkb bitmanip instructions for cryptography as ratified 291 in version 1.0 of RISC-V Cryptography Extensions Volume I 292 specification. 293 294 - const: zbkc 295 description: 296 The standard Zbkc carry-less multiply instructions as ratified 297 in version 1.0 of RISC-V Cryptography Extensions Volume I 298 specification. 299 300 - const: zbkx 301 description: 302 The standard Zbkx crossbar permutation instructions as ratified 303 in version 1.0 of RISC-V Cryptography Extensions Volume I 304 specification. 305 306 - const: zbs 307 description: | 308 The standard Zbs bit-manipulation extension for single-bit 309 instructions as ratified at commit 6d33919 ("Merge pull request #158 310 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 311 312 - const: zca 313 description: | 314 The Zca extension part of Zc* standard extensions for code size 315 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 316 RV64 as it contains no instructions") of riscv-code-size-reduction, 317 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 318 of zc.adoc to src tree."). 319 320 - const: zcb 321 description: | 322 The Zcb extension part of Zc* standard extensions for code size 323 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 324 RV64 as it contains no instructions") of riscv-code-size-reduction, 325 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 326 of zc.adoc to src tree."). 327 328 - const: zcd 329 description: | 330 The Zcd extension part of Zc* standard extensions for code size 331 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 332 RV64 as it contains no instructions") of riscv-code-size-reduction, 333 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 334 of zc.adoc to src tree."). 335 336 - const: zcf 337 description: | 338 The Zcf extension part of Zc* standard extensions for code size 339 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 340 RV64 as it contains no instructions") of riscv-code-size-reduction, 341 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 342 of zc.adoc to src tree."). 343 344 - const: zcmop 345 description: 346 The standard Zcmop extension version 1.0, as ratified in commit 347 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 348 349 - const: zfa 350 description: 351 The standard Zfa extension for additional floating point 352 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 353 riscv-isa-manual. 354 355 - const: zfbfmin 356 description: 357 The standard Zfbfmin extension which provides minimal support for 358 16-bit half-precision brain floating-point instructions, as ratified 359 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 360 361 - const: zfh 362 description: 363 The standard Zfh extension for 16-bit half-precision binary 364 floating-point instructions, as ratified in commit 64074bc ("Update 365 version numbers for Zfh/Zfinx") of riscv-isa-manual. 366 367 - const: zfhmin 368 description: 369 The standard Zfhmin extension which provides minimal support for 370 16-bit half-precision binary floating-point instructions, as ratified 371 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 372 riscv-isa-manual. 373 374 - const: ziccrse 375 description: 376 The standard Ziccrse extension which provides forward progress 377 guarantee on LR/SC sequences, as ratified in commit b1d806605f87 378 ("Updated to ratified state.") of the riscv profiles specification. 379 380 - const: zilsd 381 description: 382 The standard Zilsd extension which provides support for aligned 383 register-pair load and store operations in 32-bit instruction 384 encodings, as ratified in commit f88abf1 ("Integrating 385 load/store pair for RV32 with the main manual") of riscv-isa-manual. 386 387 - const: zclsd 388 description: 389 The Zclsd extension implements the compressed (16-bit) version of the 390 Load/Store Pair for RV32. As with Zilsd, this extension was ratified 391 in commit f88abf1 ("Integrating load/store pair for RV32 with the 392 main manual") of riscv-isa-manual. 393 394 - const: zk 395 description: 396 The standard Zk Standard Scalar cryptography extension as ratified 397 in version 1.0 of RISC-V Cryptography Extensions Volume I 398 specification. 399 400 - const: zkn 401 description: 402 The standard Zkn NIST algorithm suite extensions as ratified in 403 version 1.0 of RISC-V Cryptography Extensions Volume I 404 specification. 405 406 - const: zknd 407 description: | 408 The standard Zknd for NIST suite: AES decryption instructions as 409 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 410 specification. 411 412 - const: zkne 413 description: | 414 The standard Zkne for NIST suite: AES encryption instructions as 415 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 416 specification. 417 418 - const: zknh 419 description: | 420 The standard Zknh for NIST suite: hash function instructions as 421 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 422 specification. 423 424 - const: zkr 425 description: 426 The standard Zkr entropy source extension as ratified in version 427 1.0 of RISC-V Cryptography Extensions Volume I specification. 428 This string being present means that the CSR associated to this 429 extension is accessible at the privilege level to which that 430 device-tree has been provided. 431 432 - const: zks 433 description: 434 The standard Zks ShangMi algorithm suite extensions as ratified in 435 version 1.0 of RISC-V Cryptography Extensions Volume I 436 specification. 437 438 - const: zksed 439 description: | 440 The standard Zksed for ShangMi suite: SM4 block cipher instructions 441 as ratified in version 1.0 of RISC-V Cryptography Extensions 442 Volume I specification. 443 444 - const: zksh 445 description: | 446 The standard Zksh for ShangMi suite: SM3 hash function instructions 447 as ratified in version 1.0 of RISC-V Cryptography Extensions 448 Volume I specification. 449 450 - const: zkt 451 description: 452 The standard Zkt for data independent execution latency as ratified 453 in version 1.0 of RISC-V Cryptography Extensions Volume I 454 specification. 455 456 - const: zicbom 457 description: 458 The standard Zicbom extension for base cache management operations as 459 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 460 461 - const: zicbop 462 description: 463 The standard Zicbop extension for cache-block prefetch instructions 464 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 465 riscv-CMOs. 466 467 - const: zicboz 468 description: 469 The standard Zicboz extension for cache-block zeroing as ratified 470 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 471 472 - const: zicfilp 473 description: | 474 The standard Zicfilp extension for enforcing forward edge 475 control-flow integrity as ratified in commit 3f8e450 ("merge 476 pull request #227 from ved-rivos/0709") of riscv-cfi 477 github repo. 478 479 - const: zicfiss 480 description: | 481 The standard Zicfiss extension for enforcing backward edge 482 control-flow integrity as ratified in commit 3f8e450 ("merge 483 pull request #227 from ved-rivos/0709") of riscv-cfi 484 github repo. 485 486 - const: zicntr 487 description: 488 The standard Zicntr extension for base counters and timers, as 489 ratified in the 20191213 version of the unprivileged ISA 490 specification. 491 492 - const: zicond 493 description: 494 The standard Zicond extension for conditional arithmetic and 495 conditional-select/move operations as ratified in commit 95cf1f9 496 ("Add changes requested by Ved during signoff") of riscv-zicond. 497 498 - const: zicsr 499 description: | 500 The standard Zicsr extension for control and status register 501 instructions, as ratified in the 20191213 version of the 502 unprivileged ISA specification. 503 504 This does not include Chapter 10, "Counters", which documents 505 special case read-only CSRs, that were moved into the Zicntr and 506 Zihpm extensions after the ratification of the 20191213 version of 507 the unprivileged specification. 508 509 - const: zifencei 510 description: 511 The standard Zifencei extension for instruction-fetch fence, as 512 ratified in the 20191213 version of the unprivileged ISA 513 specification. 514 515 - const: zihintpause 516 description: 517 The standard Zihintpause extension for pause hints, as ratified in 518 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 519 520 - const: zihintntl 521 description: 522 The standard Zihintntl extension for non-temporal locality hints, as 523 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 524 riscv-isa-manual. 525 526 - const: zihpm 527 description: 528 The standard Zihpm extension for hardware performance counters, as 529 ratified in the 20191213 version of the unprivileged ISA 530 specification. 531 532 - const: zimop 533 description: 534 The standard Zimop extension version 1.0, as ratified in commit 535 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 536 537 - const: ztso 538 description: 539 The standard Ztso extension for total store ordering, as ratified 540 in commit 2e5236 ("Ztso is now ratified.") of the 541 riscv-isa-manual. 542 543 - const: zvbb 544 description: 545 The standard Zvbb extension for vectored basic bit-manipulation 546 instructions, as ratified in commit 56ed795 ("Update 547 riscv-crypto-spec-vector.adoc") of riscv-crypto. 548 549 - const: zvbc 550 description: 551 The standard Zvbc extension for vectored carryless multiplication 552 instructions, as ratified in commit 56ed795 ("Update 553 riscv-crypto-spec-vector.adoc") of riscv-crypto. 554 555 - const: zve32f 556 description: 557 The standard Zve32f extension for embedded processors, as ratified 558 in commit 6f702a2 ("Vector extensions are now ratified") of 559 riscv-v-spec. 560 561 - const: zve32x 562 description: 563 The standard Zve32x extension for embedded processors, as ratified 564 in commit 6f702a2 ("Vector extensions are now ratified") of 565 riscv-v-spec. 566 567 - const: zve64d 568 description: 569 The standard Zve64d extension for embedded processors, as ratified 570 in commit 6f702a2 ("Vector extensions are now ratified") of 571 riscv-v-spec. 572 573 - const: zve64f 574 description: 575 The standard Zve64f extension for embedded processors, as ratified 576 in commit 6f702a2 ("Vector extensions are now ratified") of 577 riscv-v-spec. 578 579 - const: zve64x 580 description: 581 The standard Zve64x extension for embedded processors, as ratified 582 in commit 6f702a2 ("Vector extensions are now ratified") of 583 riscv-v-spec. 584 585 - const: zvfbfmin 586 description: 587 The standard Zvfbfmin extension for minimal support for vectored 588 16-bit half-precision brain floating-point instructions, as ratified 589 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 590 591 - const: zvfbfwma 592 description: 593 The standard Zvfbfwma extension for vectored half-precision brain 594 floating-point widening multiply-accumulate instructions, as ratified 595 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 596 597 - const: zvfh 598 description: 599 The standard Zvfh extension for vectored half-precision 600 floating-point instructions, as ratified in commit e2ccd05 601 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 602 603 - const: zvfhmin 604 description: 605 The standard Zvfhmin extension for vectored minimal half-precision 606 floating-point instructions, as ratified in commit e2ccd05 607 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 608 609 - const: zvkb 610 description: 611 The standard Zvkb extension for vector cryptography bit-manipulation 612 instructions, as ratified in commit 56ed795 ("Update 613 riscv-crypto-spec-vector.adoc") of riscv-crypto. 614 615 - const: zvkg 616 description: 617 The standard Zvkg extension for vector GCM/GMAC instructions, as 618 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 619 of riscv-crypto. 620 621 - const: zvkn 622 description: 623 The standard Zvkn extension for NIST algorithm suite instructions, as 624 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 625 of riscv-crypto. 626 627 - const: zvknc 628 description: 629 The standard Zvknc extension for NIST algorithm suite with carryless 630 multiply instructions, as ratified in commit 56ed795 ("Update 631 riscv-crypto-spec-vector.adoc") of riscv-crypto. 632 633 - const: zvkned 634 description: 635 The standard Zvkned extension for Vector AES block cipher 636 instructions, as ratified in commit 56ed795 ("Update 637 riscv-crypto-spec-vector.adoc") of riscv-crypto. 638 639 - const: zvkng 640 description: 641 The standard Zvkng extension for NIST algorithm suite with GCM 642 instructions, as ratified in commit 56ed795 ("Update 643 riscv-crypto-spec-vector.adoc") of riscv-crypto. 644 645 - const: zvknha 646 description: | 647 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 648 hash (SHA-256 only) instructions, as ratified in commit 649 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 650 651 - const: zvknhb 652 description: | 653 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 654 hash (SHA-256 and SHA-512) instructions, as ratified in commit 655 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 656 657 - const: zvks 658 description: 659 The standard Zvks extension for ShangMi algorithm suite 660 instructions, as ratified in commit 56ed795 ("Update 661 riscv-crypto-spec-vector.adoc") of riscv-crypto. 662 663 - const: zvksc 664 description: 665 The standard Zvksc extension for ShangMi algorithm suite with 666 carryless multiplication instructions, as ratified in commit 56ed795 667 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 668 669 - const: zvksed 670 description: | 671 The standard Zvksed extension for ShangMi suite: SM4 block cipher 672 instructions, as ratified in commit 56ed795 ("Update 673 riscv-crypto-spec-vector.adoc") of riscv-crypto. 674 675 - const: zvksh 676 description: | 677 The standard Zvksh extension for ShangMi suite: SM3 secure hash 678 instructions, as ratified in commit 56ed795 ("Update 679 riscv-crypto-spec-vector.adoc") of riscv-crypto. 680 681 - const: zvksg 682 description: 683 The standard Zvksg extension for ShangMi algorithm suite with GCM 684 instructions, as ratified in commit 56ed795 ("Update 685 riscv-crypto-spec-vector.adoc") of riscv-crypto. 686 687 - const: zvkt 688 description: 689 The standard Zvkt extension for vector data-independent execution 690 latency, as ratified in commit 56ed795 ("Update 691 riscv-crypto-spec-vector.adoc") of riscv-crypto. 692 693 # vendor extensions, each extension sorted alphanumerically under the 694 # vendor they belong to. Vendors are sorted alphanumerically as well. 695 696 # Andes 697 - const: xandespmu 698 description: 699 The Andes Technology performance monitor extension for counter overflow 700 and privilege mode filtering. For more details, see Counter Related 701 Registers in the AX45MP datasheet. 702 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 703 704 # MIPS 705 - const: xmipsexectl 706 description: 707 The MIPS extension for execution control as documented in 708 https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf 709 710 # SiFive 711 - const: xsfcease 712 description: 713 SiFive CEASE Instruction Extensions Specification. 714 See more details in 715 https://www.sifive.com/document-file/freedom-u740-c000-manual 716 717 - const: xsfcflushdlone 718 description: 719 SiFive L1D Cache Flush Instruction Extensions Specification. 720 See more details in 721 https://www.sifive.com/document-file/freedom-u740-c000-manual 722 723 - const: xsfpgflushdlone 724 description: 725 SiFive PGFLUSH Instruction Extensions for the power management. The 726 CPU will flush the L1D and enter the cease state after executing 727 the instruction. 728 729 - const: xsfvqmaccdod 730 description: 731 SiFive Int8 Matrix Multiplication Extensions Specification. 732 See more details in 733 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 734 735 - const: xsfvqmaccqoq 736 description: 737 SiFive Int8 Matrix Multiplication Extensions Specification. 738 See more details in 739 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 740 741 - const: xsfvfnrclipxfqf 742 description: 743 SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. 744 See more details in 745 https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions 746 747 - const: xsfvfwmaccqqq 748 description: 749 SiFive Matrix Multiply Accumulate Instruction Extensions Specification. 750 See more details in 751 https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction 752 753 # T-HEAD 754 - const: xtheadvector 755 description: 756 The T-HEAD specific 0.7.1 vector implementation as written in 757 https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. 758 759 allOf: 760 - if: 761 contains: 762 const: d 763 then: 764 contains: 765 const: f 766 # Zcb depends on Zca 767 - if: 768 contains: 769 const: zcb 770 then: 771 contains: 772 const: zca 773 # Zcd depends on Zca and D 774 - if: 775 contains: 776 const: zcd 777 then: 778 allOf: 779 - contains: 780 const: zca 781 - contains: 782 const: d 783 # Zcf depends on Zca and F 784 - if: 785 contains: 786 const: zcf 787 then: 788 allOf: 789 - contains: 790 const: zca 791 - contains: 792 const: f 793 # Zcmop depends on Zca 794 - if: 795 contains: 796 const: zcmop 797 then: 798 contains: 799 const: zca 800 # Zfbfmin depends on F 801 - if: 802 contains: 803 const: zfbfmin 804 then: 805 contains: 806 const: f 807 # Zvfbfmin depends on V or Zve32f 808 - if: 809 contains: 810 const: zvfbfmin 811 then: 812 oneOf: 813 - contains: 814 const: v 815 - contains: 816 const: zve32f 817 # Zvfbfwma depends on Zfbfmin and Zvfbfmin 818 - if: 819 contains: 820 const: zvfbfwma 821 then: 822 allOf: 823 - contains: 824 const: zfbfmin 825 - contains: 826 const: zvfbfmin 827 # Zacas depends on Zaamo 828 - if: 829 contains: 830 const: zacas 831 then: 832 contains: 833 const: zaamo 834 835 - if: 836 contains: 837 const: zve32x 838 then: 839 contains: 840 const: zicsr 841 842 - if: 843 contains: 844 const: zve32f 845 then: 846 allOf: 847 - contains: 848 const: f 849 - contains: 850 const: zve32x 851 852 - if: 853 contains: 854 const: zve64x 855 then: 856 contains: 857 const: zve32x 858 859 - if: 860 contains: 861 const: zve64f 862 then: 863 allOf: 864 - contains: 865 const: f 866 - contains: 867 const: zve32f 868 - contains: 869 const: zve64x 870 871 - if: 872 contains: 873 const: zve64d 874 then: 875 allOf: 876 - contains: 877 const: d 878 - contains: 879 const: zve64f 880 881 - if: 882 contains: 883 anyOf: 884 - const: zvbc 885 - const: zvkn 886 - const: zvknc 887 - const: zvkng 888 - const: zvknhb 889 - const: zvksc 890 then: 891 contains: 892 anyOf: 893 - const: v 894 - const: zve64x 895 896 - if: 897 contains: 898 anyOf: 899 - const: zvbb 900 - const: zvkb 901 - const: zvkg 902 - const: zvkned 903 - const: zvknha 904 - const: zvksed 905 - const: zvksh 906 - const: zvks 907 - const: zvkt 908 then: 909 contains: 910 anyOf: 911 - const: v 912 - const: zve32x 913 # Zclsd depends on Zilsd and Zca 914 - if: 915 contains: 916 anyOf: 917 - const: zclsd 918 then: 919 contains: 920 allOf: 921 - const: zilsd 922 - const: zca 923 924allOf: 925 # Zcf extension does not exist on rv64 926 - if: 927 properties: 928 riscv,isa-extensions: 929 contains: 930 const: zcf 931 riscv,isa-base: 932 contains: 933 const: rv64i 934 then: 935 properties: 936 riscv,isa-extensions: 937 not: 938 contains: 939 const: zcf 940 # Zilsd extension does not exist on rv64 941 - if: 942 properties: 943 riscv,isa-base: 944 contains: 945 const: rv64i 946 then: 947 properties: 948 riscv,isa-extensions: 949 not: 950 contains: 951 const: zilsd 952 953additionalProperties: true 954... 955