1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27properties: 28 riscv,isa: 29 description: 30 Identifies the specific RISC-V instruction set architecture 31 supported by the hart. These are documented in the RISC-V 32 User-Level ISA document, available from 33 https://riscv.org/specifications/ 34 35 Due to revisions of the ISA specification, some deviations 36 have arisen over time. 37 Notably, riscv,isa was defined prior to the creation of the 38 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 39 implies "zicntr_zicsr_zifencei_zihpm". 40 41 While the isa strings in ISA specification are case 42 insensitive, letters in the riscv,isa string must be all 43 lowercase. 44 $ref: /schemas/types.yaml#/definitions/string 45 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 46 deprecated: true 47 48 riscv,isa-base: 49 description: 50 The base ISA implemented by this hart, as described by the 20191213 51 version of the unprivileged ISA specification. 52 enum: 53 - rv32i 54 - rv64i 55 56 riscv,isa-extensions: 57 $ref: /schemas/types.yaml#/definitions/string-array 58 minItems: 1 59 description: Extensions supported by the hart. 60 items: 61 anyOf: 62 # single letter extensions, in canonical order 63 - const: i 64 description: | 65 The base integer instruction set, as ratified in the 20191213 66 version of the unprivileged ISA specification. 67 68 This does not include Chapter 10, "Counters", which was moved into 69 the Zicntr and Zihpm extensions after the ratification of the 70 20191213 version of the unprivileged specification. 71 72 - const: m 73 description: 74 The standard M extension for integer multiplication and division, as 75 ratified in the 20191213 version of the unprivileged ISA 76 specification. 77 78 - const: a 79 description: 80 The standard A extension for atomic instructions, as ratified in the 81 20191213 version of the unprivileged ISA specification. 82 83 - const: f 84 description: 85 The standard F extension for single-precision floating point, as 86 ratified in the 20191213 version of the unprivileged ISA 87 specification. 88 89 - const: d 90 description: 91 The standard D extension for double-precision floating-point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: q 96 description: 97 The standard Q extension for quad-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: c 102 description: 103 The standard C extension for compressed instructions, as ratified in 104 the 20191213 version of the unprivileged ISA specification. 105 106 - const: b 107 description: 108 The standard B extension for bit manipulation instructions, as 109 ratified in the 20240411 version of the unprivileged ISA 110 specification. The B standard extension comprises instructions 111 provided by the Zba, Zbb, and Zbs extensions. 112 113 - const: v 114 description: 115 The standard V extension for vector operations, as ratified 116 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 117 encoding") of the riscv-v-spec. 118 119 - const: h 120 description: 121 The standard H extension for hypervisors as ratified in the RISC-V 122 Instruction Set Manual, Volume II Privileged Architecture, 123 Document Version 20211203. 124 125 # multi-letter extensions, sorted alphanumerically 126 - const: sha 127 description: | 128 The standard Sha extension for augmented hypervisor extension as 129 ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 130 ("rva23/rvb23 ratified"). 131 132 Sha captures the full set of features that are mandated to be 133 supported along with the H extension. Sha comprises the following 134 extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, 135 Shvstvecd, and Ssstateen. 136 137 - const: shcounterenw 138 description: | 139 The standard Shcounterenw extension for support writable enables 140 in hcounteren for any supported counter, as ratified in RISC-V 141 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 142 ratified state.") 143 144 - const: shgatpa 145 description: | 146 The standard Shgatpa extension indicates that for each supported 147 virtual memory scheme SvNN supported in satp, the corresponding 148 hgatp SvNNx4 mode must be supported. The hgatp mode Bare must 149 also be supported. It is ratified in RISC-V Profiles Version 1.0, 150 with commit b1d806605f87 ("Updated to ratified state.") 151 152 - const: shtvala 153 description: | 154 The standard Shtvala extension for htval be written with the 155 faulting guest physical address in all circumstances permitted by 156 the ISA. It is ratified in RISC-V Profiles Version 1.0, with 157 commit b1d806605f87 ("Updated to ratified state.") 158 159 - const: shvsatpa 160 description: | 161 The standard Shvsatpa extension for vsatp supporting all translation 162 modes supported in satp, as ratified in RISC-V Profiles Version 1.0, 163 with commit b1d806605f87 ("Updated to ratified state.") 164 165 - const: shvstvala 166 description: | 167 The standard Shvstvala extension for vstval provides all needed 168 values as ratified in RISC-V Profiles Version 1.0, with commit 169 b1d806605f87 ("Updated to ratified state.") 170 171 - const: shvstvecd 172 description: | 173 The standard Shvstvecd extension for vstvec supporting Direct mode, 174 as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 175 ("Updated to ratified state.") 176 177 - const: smaia 178 description: | 179 The standard Smaia supervisor-level extension for the advanced 180 interrupt architecture for machine-mode-visible csr and behavioural 181 changes to interrupts as frozen at commit ccbddab ("Merge pull 182 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 183 184 - const: smmpm 185 description: | 186 The standard Smmpm extension for M-mode pointer masking as 187 ratified at commit d70011dde6c2 ("Update to ratified state") 188 of riscv-j-extension. 189 190 - const: smnpm 191 description: | 192 The standard Smnpm extension for next-mode pointer masking as 193 ratified at commit d70011dde6c2 ("Update to ratified state") 194 of riscv-j-extension. 195 196 - const: smstateen 197 description: | 198 The standard Smstateen extension for controlling access to CSRs 199 added by other RISC-V extensions in H/S/VS/U/VU modes and as 200 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 201 202 - const: ssaia 203 description: | 204 The standard Ssaia supervisor-level extension for the advanced 205 interrupt architecture for supervisor-mode-visible csr and 206 behavioural changes to interrupts as frozen at commit ccbddab 207 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 208 209 - const: ssccptr 210 description: | 211 The standard Ssccptr extension for main memory (cacheability and 212 coherence) hardware page-table reads, as ratified in RISC-V 213 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 214 ratified state.") 215 216 - const: sscofpmf 217 description: | 218 The standard Sscofpmf supervisor-level extension for count overflow 219 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 220 to manually trigger workflow. (#2)") of riscv-count-overflow. 221 222 - const: sscounterenw 223 description: | 224 The standard Sscounterenw extension for support writable enables 225 in scounteren for any supported counter, as ratified in RISC-V 226 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 227 ratified state.") 228 229 - const: ssnpm 230 description: | 231 The standard Ssnpm extension for next-mode pointer masking as 232 ratified at commit d70011dde6c2 ("Update to ratified state") 233 of riscv-j-extension. 234 235 - const: ssstateen 236 description: | 237 The standard Ssstateen extension for supervisor-mode view of the 238 state-enable extension, as ratified in RISC-V Profiles Version 1.0, 239 with commit b1d806605f87 ("Updated to ratified state.") 240 241 - const: sstc 242 description: | 243 The standard Sstc supervisor-level extension for time compare as 244 ratified at commit 3f9ed34 ("Add ability to manually trigger 245 workflow. (#2)") of riscv-time-compare. 246 247 - const: sstvala 248 description: | 249 The standard Sstvala extension for stval provides all needed values 250 as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 251 ("Updated to ratified state.") 252 253 - const: sstvecd 254 description: | 255 The standard Sstvecd extension for stvec supports Direct mode as 256 ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 257 ("Updated to ratified state.") 258 259 - const: ssu64xl 260 description: | 261 The standard Ssu64xl extension for UXLEN=64 must be supported, as 262 ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 263 ("Updated to ratified state.") 264 265 - const: svade 266 description: | 267 The standard Svade supervisor-level extension for SW-managed PTE A/D 268 bit updates as ratified in the 20240213 version of the privileged 269 ISA specification. 270 271 Both Svade and Svadu extensions control the hardware behavior when 272 the PTE A/D bits need to be set. The default behavior for the four 273 possible combinations of these extensions in the device tree are: 274 1) Neither Svade nor Svadu present in DT => It is technically 275 unknown whether the platform uses Svade or Svadu. Supervisor 276 software should be prepared to handle either hardware updating 277 of the PTE A/D bits or page faults when they need updated. 278 2) Only Svade present in DT => Supervisor must assume Svade to be 279 always enabled. 280 3) Only Svadu present in DT => Supervisor must assume Svadu to be 281 always enabled. 282 4) Both Svade and Svadu present in DT => Supervisor must assume 283 Svadu turned-off at boot time. To use Svadu, supervisor must 284 explicitly enable it using the SBI FWFT extension. 285 286 - const: svadu 287 description: | 288 The standard Svadu supervisor-level extension for hardware updating 289 of PTE A/D bits as ratified in the 20240528 version of the 290 privileged ISA specification. Please refer to Svade dt-binding 291 description for more details. 292 293 - const: svinval 294 description: 295 The standard Svinval supervisor-level extension for fine-grained 296 address-translation cache invalidation as ratified in the RISC-V 297 Instruction Set Manual, Volume II Privileged Architecture, 298 Document Version 20211203. 299 300 - const: svnapot 301 description: 302 The standard Svnapot supervisor-level extensions for napot 303 translation contiguity as ratified in the RISC-V Instruction Set 304 Manual, Volume II Privileged Architecture, Document Version 305 20211203. 306 307 - const: svpbmt 308 description: 309 The standard Svpbmt supervisor-level extensions for page-based 310 memory types as ratified in the RISC-V Instruction Set Manual, 311 Volume II Privileged Architecture, Document Version 20211203. 312 313 - const: svrsw60t59b 314 description: 315 The Svrsw60t59b extension for providing two more bits[60:59] to 316 PTE/PMD entry as ratified at commit 28bde925e7a7 ("PTE Reserved 317 for SW bits 60:59") of riscv-non-isa/riscv-iommu. 318 319 - const: svvptc 320 description: 321 The standard Svvptc supervisor-level extension for 322 address-translation cache behaviour with respect to invalid entries 323 as ratified at commit 4a69197e5617 ("Update to ratified state") of 324 riscv-svvptc. 325 326 - const: za64rs 327 description: 328 The standard Za64rs extension for reservation set size of at most 329 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit 330 b1d806605f87 ("Updated to ratified state.") 331 332 - const: zaamo 333 description: | 334 The standard Zaamo extension for atomic memory operations as 335 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 336 (#1304)") of the unprivileged ISA specification. 337 338 - const: zabha 339 description: | 340 The Zabha extension for Byte and Halfword Atomic Memory Operations 341 as ratified at commit 49f49c842ff9 ("Update to Rafified state") of 342 riscv-zabha. 343 344 - const: zacas 345 description: | 346 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 347 is supported as ratified at commit 5059e0ca641c ("update to 348 ratified") of the riscv-zacas. 349 350 - const: zalasr 351 description: | 352 The standard Zalasr extension for load-acquire/store-release as frozen 353 at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. 354 355 - const: zalrsc 356 description: | 357 The standard Zalrsc extension for load-reserved/store-conditional as 358 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 359 (#1304)") of the unprivileged ISA specification. 360 361 - const: zawrs 362 description: | 363 The Zawrs extension for entering a low-power state or for trapping 364 to a hypervisor while waiting on a store to a memory location, as 365 ratified in commit 98918c844281 ("Merge pull request #1217 from 366 riscv/zawrs") of riscv-isa-manual. 367 368 - const: zba 369 description: | 370 The standard Zba bit-manipulation extension for address generation 371 acceleration instructions as ratified at commit 6d33919 ("Merge pull 372 request #158 from hirooih/clmul-fix-loop-end-condition") of 373 riscv-bitmanip. 374 375 - const: zbb 376 description: | 377 The standard Zbb bit-manipulation extension for basic bit-manipulation 378 as ratified at commit 6d33919 ("Merge pull request #158 from 379 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 380 381 - const: zbc 382 description: | 383 The standard Zbc bit-manipulation extension for carry-less 384 multiplication as ratified at commit 6d33919 ("Merge pull request 385 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 386 387 - const: zbkb 388 description: 389 The standard Zbkb bitmanip instructions for cryptography as ratified 390 in version 1.0 of RISC-V Cryptography Extensions Volume I 391 specification. 392 393 - const: zbkc 394 description: 395 The standard Zbkc carry-less multiply instructions as ratified 396 in version 1.0 of RISC-V Cryptography Extensions Volume I 397 specification. 398 399 - const: zbkx 400 description: 401 The standard Zbkx crossbar permutation instructions as ratified 402 in version 1.0 of RISC-V Cryptography Extensions Volume I 403 specification. 404 405 - const: zbs 406 description: | 407 The standard Zbs bit-manipulation extension for single-bit 408 instructions as ratified at commit 6d33919 ("Merge pull request #158 409 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 410 411 - const: zca 412 description: | 413 The Zca extension part of Zc* standard extensions for code size 414 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 415 RV64 as it contains no instructions") of riscv-code-size-reduction, 416 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 417 of zc.adoc to src tree."). 418 419 - const: zcb 420 description: | 421 The Zcb extension part of Zc* standard extensions for code size 422 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 423 RV64 as it contains no instructions") of riscv-code-size-reduction, 424 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 425 of zc.adoc to src tree."). 426 427 - const: zcd 428 description: | 429 The Zcd extension part of Zc* standard extensions for code size 430 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 431 RV64 as it contains no instructions") of riscv-code-size-reduction, 432 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 433 of zc.adoc to src tree."). 434 435 - const: zcf 436 description: | 437 The Zcf extension part of Zc* standard extensions for code size 438 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 439 RV64 as it contains no instructions") of riscv-code-size-reduction, 440 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 441 of zc.adoc to src tree."). 442 443 - const: zcmop 444 description: 445 The standard Zcmop extension version 1.0, as ratified in commit 446 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 447 448 - const: zfa 449 description: 450 The standard Zfa extension for additional floating point 451 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 452 riscv-isa-manual. 453 454 - const: zfbfmin 455 description: 456 The standard Zfbfmin extension which provides minimal support for 457 16-bit half-precision brain floating-point instructions, as ratified 458 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 459 460 - const: zfh 461 description: 462 The standard Zfh extension for 16-bit half-precision binary 463 floating-point instructions, as ratified in commit 64074bc ("Update 464 version numbers for Zfh/Zfinx") of riscv-isa-manual. 465 466 - const: zfhmin 467 description: 468 The standard Zfhmin extension which provides minimal support for 469 16-bit half-precision binary floating-point instructions, as ratified 470 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 471 riscv-isa-manual. 472 473 - const: ziccamoa 474 description: 475 The standard Ziccamoa extension for main memory (cacheability and 476 coherence) must support all atomics in A, as ratified in RISC-V 477 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 478 ratified state.") 479 480 - const: ziccif 481 description: 482 The standard Ziccif extension for main memory (cacheability and 483 coherence) instruction fetch atomicity, as ratified in RISC-V 484 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 485 ratified state.") 486 487 - const: zicclsm 488 description: 489 The standard Zicclsm extension for main memory (cacheability and 490 coherence) must support misaligned loads and stores, as ratified 491 in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated 492 to ratified state.") 493 494 - const: ziccrse 495 description: 496 The standard Ziccrse extension which provides forward progress 497 guarantee on LR/SC sequences, as ratified in commit b1d806605f87 498 ("Updated to ratified state.") of the riscv profiles specification. 499 500 - const: zilsd 501 description: 502 The standard Zilsd extension which provides support for aligned 503 register-pair load and store operations in 32-bit instruction 504 encodings, as ratified in commit f88abf1 ("Integrating 505 load/store pair for RV32 with the main manual") of riscv-isa-manual. 506 507 - const: zclsd 508 description: 509 The Zclsd extension implements the compressed (16-bit) version of the 510 Load/Store Pair for RV32. As with Zilsd, this extension was ratified 511 in commit f88abf1 ("Integrating load/store pair for RV32 with the 512 main manual") of riscv-isa-manual. 513 514 - const: zk 515 description: 516 The standard Zk Standard Scalar cryptography extension as ratified 517 in version 1.0 of RISC-V Cryptography Extensions Volume I 518 specification. 519 520 - const: zkn 521 description: 522 The standard Zkn NIST algorithm suite extensions as ratified in 523 version 1.0 of RISC-V Cryptography Extensions Volume I 524 specification. 525 526 - const: zknd 527 description: | 528 The standard Zknd for NIST suite: AES decryption instructions as 529 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 530 specification. 531 532 - const: zkne 533 description: | 534 The standard Zkne for NIST suite: AES encryption instructions as 535 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 536 specification. 537 538 - const: zknh 539 description: | 540 The standard Zknh for NIST suite: hash function instructions as 541 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 542 specification. 543 544 - const: zkr 545 description: 546 The standard Zkr entropy source extension as ratified in version 547 1.0 of RISC-V Cryptography Extensions Volume I specification. 548 This string being present means that the CSR associated to this 549 extension is accessible at the privilege level to which that 550 device-tree has been provided. 551 552 - const: zks 553 description: 554 The standard Zks ShangMi algorithm suite extensions as ratified in 555 version 1.0 of RISC-V Cryptography Extensions Volume I 556 specification. 557 558 - const: zksed 559 description: | 560 The standard Zksed for ShangMi suite: SM4 block cipher instructions 561 as ratified in version 1.0 of RISC-V Cryptography Extensions 562 Volume I specification. 563 564 - const: zksh 565 description: | 566 The standard Zksh for ShangMi suite: SM3 hash function instructions 567 as ratified in version 1.0 of RISC-V Cryptography Extensions 568 Volume I specification. 569 570 - const: zkt 571 description: 572 The standard Zkt for data independent execution latency as ratified 573 in version 1.0 of RISC-V Cryptography Extensions Volume I 574 specification. 575 576 - const: zicbom 577 description: 578 The standard Zicbom extension for base cache management operations as 579 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 580 581 - const: zicbop 582 description: 583 The standard Zicbop extension for cache-block prefetch instructions 584 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 585 riscv-CMOs. 586 587 - const: zicboz 588 description: 589 The standard Zicboz extension for cache-block zeroing as ratified 590 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 591 592 - const: zicfilp 593 description: | 594 The standard Zicfilp extension for enforcing forward edge 595 control-flow integrity as ratified in commit 3f8e450 ("merge 596 pull request #227 from ved-rivos/0709") of riscv-cfi 597 github repo. 598 599 - const: zicfiss 600 description: | 601 The standard Zicfiss extension for enforcing backward edge 602 control-flow integrity as ratified in commit 3f8e450 ("merge 603 pull request #227 from ved-rivos/0709") of riscv-cfi 604 github repo. 605 606 - const: zicntr 607 description: 608 The standard Zicntr extension for base counters and timers, as 609 ratified in the 20191213 version of the unprivileged ISA 610 specification. 611 612 - const: zicond 613 description: 614 The standard Zicond extension for conditional arithmetic and 615 conditional-select/move operations as ratified in commit 95cf1f9 616 ("Add changes requested by Ved during signoff") of riscv-zicond. 617 618 - const: zicsr 619 description: | 620 The standard Zicsr extension for control and status register 621 instructions, as ratified in the 20191213 version of the 622 unprivileged ISA specification. 623 624 This does not include Chapter 10, "Counters", which documents 625 special case read-only CSRs, that were moved into the Zicntr and 626 Zihpm extensions after the ratification of the 20191213 version of 627 the unprivileged specification. 628 629 - const: zifencei 630 description: 631 The standard Zifencei extension for instruction-fetch fence, as 632 ratified in the 20191213 version of the unprivileged ISA 633 specification. 634 635 - const: zihintpause 636 description: 637 The standard Zihintpause extension for pause hints, as ratified in 638 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 639 640 - const: zihintntl 641 description: 642 The standard Zihintntl extension for non-temporal locality hints, as 643 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 644 riscv-isa-manual. 645 646 - const: zihpm 647 description: 648 The standard Zihpm extension for hardware performance counters, as 649 ratified in the 20191213 version of the unprivileged ISA 650 specification. 651 652 - const: zimop 653 description: 654 The standard Zimop extension version 1.0, as ratified in commit 655 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 656 657 - const: ztso 658 description: 659 The standard Ztso extension for total store ordering, as ratified 660 in commit 2e5236 ("Ztso is now ratified.") of the 661 riscv-isa-manual. 662 663 - const: zvbb 664 description: 665 The standard Zvbb extension for vectored basic bit-manipulation 666 instructions, as ratified in commit 56ed795 ("Update 667 riscv-crypto-spec-vector.adoc") of riscv-crypto. 668 669 - const: zvbc 670 description: 671 The standard Zvbc extension for vectored carryless multiplication 672 instructions, as ratified in commit 56ed795 ("Update 673 riscv-crypto-spec-vector.adoc") of riscv-crypto. 674 675 - const: zve32f 676 description: 677 The standard Zve32f extension for embedded processors, as ratified 678 in commit 6f702a2 ("Vector extensions are now ratified") of 679 riscv-v-spec. 680 681 - const: zve32x 682 description: 683 The standard Zve32x extension for embedded processors, as ratified 684 in commit 6f702a2 ("Vector extensions are now ratified") of 685 riscv-v-spec. 686 687 - const: zve64d 688 description: 689 The standard Zve64d extension for embedded processors, as ratified 690 in commit 6f702a2 ("Vector extensions are now ratified") of 691 riscv-v-spec. 692 693 - const: zve64f 694 description: 695 The standard Zve64f extension for embedded processors, as ratified 696 in commit 6f702a2 ("Vector extensions are now ratified") of 697 riscv-v-spec. 698 699 - const: zve64x 700 description: 701 The standard Zve64x extension for embedded processors, as ratified 702 in commit 6f702a2 ("Vector extensions are now ratified") of 703 riscv-v-spec. 704 705 - const: zvfbfmin 706 description: 707 The standard Zvfbfmin extension for minimal support for vectored 708 16-bit half-precision brain floating-point instructions, as ratified 709 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 710 711 - const: zvfbfwma 712 description: 713 The standard Zvfbfwma extension for vectored half-precision brain 714 floating-point widening multiply-accumulate instructions, as ratified 715 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 716 717 - const: zvfh 718 description: 719 The standard Zvfh extension for vectored half-precision 720 floating-point instructions, as ratified in commit e2ccd05 721 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 722 723 - const: zvfhmin 724 description: 725 The standard Zvfhmin extension for vectored minimal half-precision 726 floating-point instructions, as ratified in commit e2ccd05 727 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 728 729 - const: zvkb 730 description: 731 The standard Zvkb extension for vector cryptography bit-manipulation 732 instructions, as ratified in commit 56ed795 ("Update 733 riscv-crypto-spec-vector.adoc") of riscv-crypto. 734 735 - const: zvkg 736 description: 737 The standard Zvkg extension for vector GCM/GMAC instructions, as 738 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 739 of riscv-crypto. 740 741 - const: zvkn 742 description: 743 The standard Zvkn extension for NIST algorithm suite instructions, as 744 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 745 of riscv-crypto. 746 747 - const: zvknc 748 description: 749 The standard Zvknc extension for NIST algorithm suite with carryless 750 multiply instructions, as ratified in commit 56ed795 ("Update 751 riscv-crypto-spec-vector.adoc") of riscv-crypto. 752 753 - const: zvkned 754 description: 755 The standard Zvkned extension for Vector AES block cipher 756 instructions, as ratified in commit 56ed795 ("Update 757 riscv-crypto-spec-vector.adoc") of riscv-crypto. 758 759 - const: zvkng 760 description: 761 The standard Zvkng extension for NIST algorithm suite with GCM 762 instructions, as ratified in commit 56ed795 ("Update 763 riscv-crypto-spec-vector.adoc") of riscv-crypto. 764 765 - const: zvknha 766 description: | 767 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 768 hash (SHA-256 only) instructions, as ratified in commit 769 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 770 771 - const: zvknhb 772 description: | 773 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 774 hash (SHA-256 and SHA-512) instructions, as ratified in commit 775 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 776 777 - const: zvks 778 description: 779 The standard Zvks extension for ShangMi algorithm suite 780 instructions, as ratified in commit 56ed795 ("Update 781 riscv-crypto-spec-vector.adoc") of riscv-crypto. 782 783 - const: zvksc 784 description: 785 The standard Zvksc extension for ShangMi algorithm suite with 786 carryless multiplication instructions, as ratified in commit 56ed795 787 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 788 789 - const: zvksed 790 description: | 791 The standard Zvksed extension for ShangMi suite: SM4 block cipher 792 instructions, as ratified in commit 56ed795 ("Update 793 riscv-crypto-spec-vector.adoc") of riscv-crypto. 794 795 - const: zvksh 796 description: | 797 The standard Zvksh extension for ShangMi suite: SM3 secure hash 798 instructions, as ratified in commit 56ed795 ("Update 799 riscv-crypto-spec-vector.adoc") of riscv-crypto. 800 801 - const: zvksg 802 description: 803 The standard Zvksg extension for ShangMi algorithm suite with GCM 804 instructions, as ratified in commit 56ed795 ("Update 805 riscv-crypto-spec-vector.adoc") of riscv-crypto. 806 807 - const: zvkt 808 description: 809 The standard Zvkt extension for vector data-independent execution 810 latency, as ratified in commit 56ed795 ("Update 811 riscv-crypto-spec-vector.adoc") of riscv-crypto. 812 813 # vendor extensions, each extension sorted alphanumerically under the 814 # vendor they belong to. Vendors are sorted alphanumerically as well. 815 816 # Andes 817 - const: xandespmu 818 description: 819 The Andes Technology performance monitor extension for counter overflow 820 and privilege mode filtering. For more details, see Counter Related 821 Registers in the AX45MP datasheet. 822 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 823 824 # MIPS 825 - const: xmipsexectl 826 description: 827 The MIPS extension for execution control as documented in 828 https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf 829 830 # SiFive 831 - const: xsfcease 832 description: 833 SiFive CEASE Instruction Extensions Specification. 834 See more details in 835 https://www.sifive.com/document-file/freedom-u740-c000-manual 836 837 - const: xsfcflushdlone 838 description: 839 SiFive L1D Cache Flush Instruction Extensions Specification. 840 See more details in 841 https://www.sifive.com/document-file/freedom-u740-c000-manual 842 843 - const: xsfpgflushdlone 844 description: 845 SiFive PGFLUSH Instruction Extensions for the power management. The 846 CPU will flush the L1D and enter the cease state after executing 847 the instruction. 848 849 - const: xsfvqmaccdod 850 description: 851 SiFive Int8 Matrix Multiplication Extensions Specification. 852 See more details in 853 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 854 855 - const: xsfvqmaccqoq 856 description: 857 SiFive Int8 Matrix Multiplication Extensions Specification. 858 See more details in 859 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 860 861 - const: xsfvfnrclipxfqf 862 description: 863 SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. 864 See more details in 865 https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions 866 867 - const: xsfvfwmaccqqq 868 description: 869 SiFive Matrix Multiply Accumulate Instruction Extensions Specification. 870 See more details in 871 https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction 872 873 # T-HEAD 874 - const: xtheadvector 875 description: 876 The T-HEAD specific 0.7.1 vector implementation as written in 877 https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. 878 879 allOf: 880 - if: 881 contains: 882 const: d 883 then: 884 contains: 885 const: f 886 # B comprises Zba, Zbb, and Zbs 887 - if: 888 contains: 889 const: b 890 then: 891 allOf: 892 - contains: 893 const: zba 894 - contains: 895 const: zbb 896 - contains: 897 const: zbs 898 # Zba, Zbb, Zbs together require B 899 - if: 900 allOf: 901 - contains: 902 const: zba 903 - contains: 904 const: zbb 905 - contains: 906 const: zbs 907 then: 908 contains: 909 const: b 910 # Za64rs and Ziccrse depend on Zalrsc or A 911 - if: 912 contains: 913 anyOf: 914 - const: za64rs 915 - const: ziccrse 916 then: 917 oneOf: 918 - contains: 919 const: zalrsc 920 - contains: 921 const: a 922 # Zcb depends on Zca 923 - if: 924 contains: 925 const: zcb 926 then: 927 contains: 928 const: zca 929 # Zcd depends on Zca and D 930 - if: 931 contains: 932 const: zcd 933 then: 934 allOf: 935 - contains: 936 const: zca 937 - contains: 938 const: d 939 # Zcf depends on Zca and F 940 - if: 941 contains: 942 const: zcf 943 then: 944 allOf: 945 - contains: 946 const: zca 947 - contains: 948 const: f 949 # Zcmop depends on Zca 950 - if: 951 contains: 952 const: zcmop 953 then: 954 contains: 955 const: zca 956 # Zfbfmin depends on F 957 - if: 958 contains: 959 const: zfbfmin 960 then: 961 contains: 962 const: f 963 # Ziccamoa depends on Zaamo or A 964 - if: 965 contains: 966 const: ziccamoa 967 then: 968 oneOf: 969 - contains: 970 const: zaamo 971 - contains: 972 const: a 973 # Zvfbfmin depends on V or Zve32f 974 - if: 975 contains: 976 const: zvfbfmin 977 then: 978 oneOf: 979 - contains: 980 const: v 981 - contains: 982 const: zve32f 983 # Zvfbfwma depends on Zfbfmin and Zvfbfmin 984 - if: 985 contains: 986 const: zvfbfwma 987 then: 988 allOf: 989 - contains: 990 const: zfbfmin 991 - contains: 992 const: zvfbfmin 993 # Zacas depends on Zaamo 994 - if: 995 contains: 996 const: zacas 997 then: 998 contains: 999 const: zaamo 1000 1001 - if: 1002 contains: 1003 const: zve32x 1004 then: 1005 contains: 1006 const: zicsr 1007 1008 - if: 1009 contains: 1010 const: zve32f 1011 then: 1012 allOf: 1013 - contains: 1014 const: f 1015 - contains: 1016 const: zve32x 1017 1018 - if: 1019 contains: 1020 const: zve64x 1021 then: 1022 contains: 1023 const: zve32x 1024 1025 - if: 1026 contains: 1027 const: zve64f 1028 then: 1029 allOf: 1030 - contains: 1031 const: f 1032 - contains: 1033 const: zve32f 1034 - contains: 1035 const: zve64x 1036 1037 - if: 1038 contains: 1039 const: zve64d 1040 then: 1041 allOf: 1042 - contains: 1043 const: d 1044 - contains: 1045 const: zve64f 1046 1047 - if: 1048 contains: 1049 anyOf: 1050 - const: zvbc 1051 - const: zvkn 1052 - const: zvknc 1053 - const: zvkng 1054 - const: zvknhb 1055 - const: zvksc 1056 then: 1057 contains: 1058 anyOf: 1059 - const: v 1060 - const: zve64x 1061 1062 - if: 1063 contains: 1064 anyOf: 1065 - const: zvbb 1066 - const: zvkb 1067 - const: zvkg 1068 - const: zvkned 1069 - const: zvknha 1070 - const: zvksed 1071 - const: zvksh 1072 - const: zvks 1073 - const: zvkt 1074 then: 1075 contains: 1076 anyOf: 1077 - const: v 1078 - const: zve32x 1079 # Zclsd depends on Zilsd and Zca 1080 - if: 1081 contains: 1082 anyOf: 1083 - const: zclsd 1084 then: 1085 contains: 1086 allOf: 1087 - const: zilsd 1088 - const: zca 1089 1090allOf: 1091 # Zcf extension does not exist on rv64 1092 - if: 1093 properties: 1094 riscv,isa-extensions: 1095 contains: 1096 const: zcf 1097 riscv,isa-base: 1098 contains: 1099 const: rv64i 1100 then: 1101 properties: 1102 riscv,isa-extensions: 1103 not: 1104 contains: 1105 const: zcf 1106 # Zilsd extension does not exist on rv64 1107 - if: 1108 properties: 1109 riscv,isa-base: 1110 contains: 1111 const: rv64i 1112 then: 1113 properties: 1114 riscv,isa-extensions: 1115 not: 1116 contains: 1117 const: zilsd 1118 1119additionalProperties: true 1120... 1121