1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27select: 28 properties: 29 compatible: 30 contains: 31 const: riscv 32 33properties: 34 riscv,isa: 35 description: 36 Identifies the specific RISC-V instruction set architecture 37 supported by the hart. These are documented in the RISC-V 38 User-Level ISA document, available from 39 https://riscv.org/specifications/ 40 41 Due to revisions of the ISA specification, some deviations 42 have arisen over time. 43 Notably, riscv,isa was defined prior to the creation of the 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45 implies "zicntr_zicsr_zifencei_zihpm". 46 47 While the isa strings in ISA specification are case 48 insensitive, letters in the riscv,isa string must be all 49 lowercase. 50 $ref: /schemas/types.yaml#/definitions/string 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 52 deprecated: true 53 54 riscv,isa-base: 55 description: 56 The base ISA implemented by this hart, as described by the 20191213 57 version of the unprivileged ISA specification. 58 enum: 59 - rv32i 60 - rv64i 61 62 riscv,isa-extensions: 63 $ref: /schemas/types.yaml#/definitions/string-array 64 minItems: 1 65 description: Extensions supported by the hart. 66 items: 67 anyOf: 68 # single letter extensions, in canonical order 69 - const: i 70 description: | 71 The base integer instruction set, as ratified in the 20191213 72 version of the unprivileged ISA specification. 73 74 This does not include Chapter 10, "Counters", which was moved into 75 the Zicntr and Zihpm extensions after the ratification of the 76 20191213 version of the unprivileged specification. 77 78 - const: m 79 description: 80 The standard M extension for integer multiplication and division, as 81 ratified in the 20191213 version of the unprivileged ISA 82 specification. 83 84 - const: a 85 description: 86 The standard A extension for atomic instructions, as ratified in the 87 20191213 version of the unprivileged ISA specification. 88 89 - const: f 90 description: 91 The standard F extension for single-precision floating point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: d 96 description: 97 The standard D extension for double-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: q 102 description: 103 The standard Q extension for quad-precision floating-point, as 104 ratified in the 20191213 version of the unprivileged ISA 105 specification. 106 107 - const: c 108 description: 109 The standard C extension for compressed instructions, as ratified in 110 the 20191213 version of the unprivileged ISA specification. 111 112 - const: v 113 description: 114 The standard V extension for vector operations, as ratified 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116 encoding") of the riscv-v-spec. 117 118 - const: h 119 description: 120 The standard H extension for hypervisors as ratified in the 20191213 121 version of the privileged ISA specification. 122 123 # multi-letter extensions, sorted alphanumerically 124 - const: smaia 125 description: | 126 The standard Smaia supervisor-level extension for the advanced 127 interrupt architecture for machine-mode-visible csr and behavioural 128 changes to interrupts as frozen at commit ccbddab ("Merge pull 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130 131 - const: smstateen 132 description: | 133 The standard Smstateen extension for controlling access to CSRs 134 added by other RISC-V extensions in H/S/VS/U/VU modes and as 135 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 136 137 - const: ssaia 138 description: | 139 The standard Ssaia supervisor-level extension for the advanced 140 interrupt architecture for supervisor-mode-visible csr and 141 behavioural changes to interrupts as frozen at commit ccbddab 142 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 143 144 - const: sscofpmf 145 description: | 146 The standard Sscofpmf supervisor-level extension for count overflow 147 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 148 to manually trigger workflow. (#2)") of riscv-count-overflow. 149 150 - const: sstc 151 description: | 152 The standard Sstc supervisor-level extension for time compare as 153 ratified at commit 3f9ed34 ("Add ability to manually trigger 154 workflow. (#2)") of riscv-time-compare. 155 156 - const: svade 157 description: | 158 The standard Svade supervisor-level extension for SW-managed PTE A/D 159 bit updates as ratified in the 20240213 version of the privileged 160 ISA specification. 161 162 Both Svade and Svadu extensions control the hardware behavior when 163 the PTE A/D bits need to be set. The default behavior for the four 164 possible combinations of these extensions in the device tree are: 165 1) Neither Svade nor Svadu present in DT => It is technically 166 unknown whether the platform uses Svade or Svadu. Supervisor 167 software should be prepared to handle either hardware updating 168 of the PTE A/D bits or page faults when they need updated. 169 2) Only Svade present in DT => Supervisor must assume Svade to be 170 always enabled. 171 3) Only Svadu present in DT => Supervisor must assume Svadu to be 172 always enabled. 173 4) Both Svade and Svadu present in DT => Supervisor must assume 174 Svadu turned-off at boot time. To use Svadu, supervisor must 175 explicitly enable it using the SBI FWFT extension. 176 177 - const: svadu 178 description: | 179 The standard Svadu supervisor-level extension for hardware updating 180 of PTE A/D bits as ratified in the 20240528 version of the 181 privileged ISA specification. Please refer to Svade dt-binding 182 description for more details. 183 184 - const: svinval 185 description: 186 The standard Svinval supervisor-level extension for fine-grained 187 address-translation cache invalidation as ratified in the 20191213 188 version of the privileged ISA specification. 189 190 - const: svnapot 191 description: 192 The standard Svnapot supervisor-level extensions for napot 193 translation contiguity as ratified in the 20191213 version of the 194 privileged ISA specification. 195 196 - const: svpbmt 197 description: 198 The standard Svpbmt supervisor-level extensions for page-based 199 memory types as ratified in the 20191213 version of the privileged 200 ISA specification. 201 202 - const: svvptc 203 description: 204 The standard Svvptc supervisor-level extension for 205 address-translation cache behaviour with respect to invalid entries 206 as ratified at commit 4a69197e5617 ("Update to ratified state") of 207 riscv-svvptc. 208 209 - const: zacas 210 description: | 211 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 212 is supported as ratified at commit 5059e0ca641c ("update to 213 ratified") of the riscv-zacas. 214 215 - const: zawrs 216 description: | 217 The Zawrs extension for entering a low-power state or for trapping 218 to a hypervisor while waiting on a store to a memory location, as 219 ratified in commit 98918c844281 ("Merge pull request #1217 from 220 riscv/zawrs") of riscv-isa-manual. 221 222 - const: zba 223 description: | 224 The standard Zba bit-manipulation extension for address generation 225 acceleration instructions as ratified at commit 6d33919 ("Merge pull 226 request #158 from hirooih/clmul-fix-loop-end-condition") of 227 riscv-bitmanip. 228 229 - const: zbb 230 description: | 231 The standard Zbb bit-manipulation extension for basic bit-manipulation 232 as ratified at commit 6d33919 ("Merge pull request #158 from 233 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 234 235 - const: zbc 236 description: | 237 The standard Zbc bit-manipulation extension for carry-less 238 multiplication as ratified at commit 6d33919 ("Merge pull request 239 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 240 241 - const: zbkb 242 description: 243 The standard Zbkb bitmanip instructions for cryptography as ratified 244 in version 1.0 of RISC-V Cryptography Extensions Volume I 245 specification. 246 247 - const: zbkc 248 description: 249 The standard Zbkc carry-less multiply instructions as ratified 250 in version 1.0 of RISC-V Cryptography Extensions Volume I 251 specification. 252 253 - const: zbkx 254 description: 255 The standard Zbkx crossbar permutation instructions as ratified 256 in version 1.0 of RISC-V Cryptography Extensions Volume I 257 specification. 258 259 - const: zbs 260 description: | 261 The standard Zbs bit-manipulation extension for single-bit 262 instructions as ratified at commit 6d33919 ("Merge pull request #158 263 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 264 265 - const: zca 266 description: | 267 The Zca extension part of Zc* standard extensions for code size 268 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 269 RV64 as it contains no instructions") of riscv-code-size-reduction, 270 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 271 of zc.adoc to src tree."). 272 273 - const: zcb 274 description: | 275 The Zcb extension part of Zc* standard extensions for code size 276 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 277 RV64 as it contains no instructions") of riscv-code-size-reduction, 278 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 279 of zc.adoc to src tree."). 280 281 - const: zcd 282 description: | 283 The Zcd extension part of Zc* standard extensions for code size 284 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 285 RV64 as it contains no instructions") of riscv-code-size-reduction, 286 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 287 of zc.adoc to src tree."). 288 289 - const: zcf 290 description: | 291 The Zcf extension part of Zc* standard extensions for code size 292 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 293 RV64 as it contains no instructions") of riscv-code-size-reduction, 294 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 295 of zc.adoc to src tree."). 296 297 - const: zcmop 298 description: 299 The standard Zcmop extension version 1.0, as ratified in commit 300 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 301 302 - const: zfa 303 description: 304 The standard Zfa extension for additional floating point 305 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 306 riscv-isa-manual. 307 308 - const: zfh 309 description: 310 The standard Zfh extension for 16-bit half-precision binary 311 floating-point instructions, as ratified in commit 64074bc ("Update 312 version numbers for Zfh/Zfinx") of riscv-isa-manual. 313 314 - const: zfhmin 315 description: 316 The standard Zfhmin extension which provides minimal support for 317 16-bit half-precision binary floating-point instructions, as ratified 318 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 319 riscv-isa-manual. 320 321 - const: zk 322 description: 323 The standard Zk Standard Scalar cryptography extension as ratified 324 in version 1.0 of RISC-V Cryptography Extensions Volume I 325 specification. 326 327 - const: zkn 328 description: 329 The standard Zkn NIST algorithm suite extensions as ratified in 330 version 1.0 of RISC-V Cryptography Extensions Volume I 331 specification. 332 333 - const: zknd 334 description: | 335 The standard Zknd for NIST suite: AES decryption instructions as 336 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 337 specification. 338 339 - const: zkne 340 description: | 341 The standard Zkne for NIST suite: AES encryption instructions as 342 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 343 specification. 344 345 - const: zknh 346 description: | 347 The standard Zknh for NIST suite: hash function instructions as 348 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 349 specification. 350 351 - const: zkr 352 description: 353 The standard Zkr entropy source extension as ratified in version 354 1.0 of RISC-V Cryptography Extensions Volume I specification. 355 This string being present means that the CSR associated to this 356 extension is accessible at the privilege level to which that 357 device-tree has been provided. 358 359 - const: zks 360 description: 361 The standard Zks ShangMi algorithm suite extensions as ratified in 362 version 1.0 of RISC-V Cryptography Extensions Volume I 363 specification. 364 365 - const: zksed 366 description: | 367 The standard Zksed for ShangMi suite: SM4 block cipher instructions 368 as ratified in version 1.0 of RISC-V Cryptography Extensions 369 Volume I specification. 370 371 - const: zksh 372 description: | 373 The standard Zksh for ShangMi suite: SM3 hash function instructions 374 as ratified in version 1.0 of RISC-V Cryptography Extensions 375 Volume I specification. 376 377 - const: zkt 378 description: 379 The standard Zkt for data independent execution latency as ratified 380 in version 1.0 of RISC-V Cryptography Extensions Volume I 381 specification. 382 383 - const: zicbom 384 description: 385 The standard Zicbom extension for base cache management operations as 386 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 387 388 - const: zicbop 389 description: 390 The standard Zicbop extension for cache-block prefetch instructions 391 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 392 riscv-CMOs. 393 394 - const: zicboz 395 description: 396 The standard Zicboz extension for cache-block zeroing as ratified 397 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 398 399 - const: zicntr 400 description: 401 The standard Zicntr extension for base counters and timers, as 402 ratified in the 20191213 version of the unprivileged ISA 403 specification. 404 405 - const: zicond 406 description: 407 The standard Zicond extension for conditional arithmetic and 408 conditional-select/move operations as ratified in commit 95cf1f9 409 ("Add changes requested by Ved during signoff") of riscv-zicond. 410 411 - const: zicsr 412 description: | 413 The standard Zicsr extension for control and status register 414 instructions, as ratified in the 20191213 version of the 415 unprivileged ISA specification. 416 417 This does not include Chapter 10, "Counters", which documents 418 special case read-only CSRs, that were moved into the Zicntr and 419 Zihpm extensions after the ratification of the 20191213 version of 420 the unprivileged specification. 421 422 - const: zifencei 423 description: 424 The standard Zifencei extension for instruction-fetch fence, as 425 ratified in the 20191213 version of the unprivileged ISA 426 specification. 427 428 - const: zihintpause 429 description: 430 The standard Zihintpause extension for pause hints, as ratified in 431 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 432 433 - const: zihintntl 434 description: 435 The standard Zihintntl extension for non-temporal locality hints, as 436 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 437 riscv-isa-manual. 438 439 - const: zihpm 440 description: 441 The standard Zihpm extension for hardware performance counters, as 442 ratified in the 20191213 version of the unprivileged ISA 443 specification. 444 445 - const: zimop 446 description: 447 The standard Zimop extension version 1.0, as ratified in commit 448 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 449 450 - const: ztso 451 description: 452 The standard Ztso extension for total store ordering, as ratified 453 in commit 2e5236 ("Ztso is now ratified.") of the 454 riscv-isa-manual. 455 456 - const: zvbb 457 description: 458 The standard Zvbb extension for vectored basic bit-manipulation 459 instructions, as ratified in commit 56ed795 ("Update 460 riscv-crypto-spec-vector.adoc") of riscv-crypto. 461 462 - const: zvbc 463 description: 464 The standard Zvbc extension for vectored carryless multiplication 465 instructions, as ratified in commit 56ed795 ("Update 466 riscv-crypto-spec-vector.adoc") of riscv-crypto. 467 468 - const: zve32f 469 description: 470 The standard Zve32f extension for embedded processors, as ratified 471 in commit 6f702a2 ("Vector extensions are now ratified") of 472 riscv-v-spec. 473 474 - const: zve32x 475 description: 476 The standard Zve32x extension for embedded processors, as ratified 477 in commit 6f702a2 ("Vector extensions are now ratified") of 478 riscv-v-spec. 479 480 - const: zve64d 481 description: 482 The standard Zve64d extension for embedded processors, as ratified 483 in commit 6f702a2 ("Vector extensions are now ratified") of 484 riscv-v-spec. 485 486 - const: zve64f 487 description: 488 The standard Zve64f extension for embedded processors, as ratified 489 in commit 6f702a2 ("Vector extensions are now ratified") of 490 riscv-v-spec. 491 492 - const: zve64x 493 description: 494 The standard Zve64x extension for embedded processors, as ratified 495 in commit 6f702a2 ("Vector extensions are now ratified") of 496 riscv-v-spec. 497 498 - const: zvfh 499 description: 500 The standard Zvfh extension for vectored half-precision 501 floating-point instructions, as ratified in commit e2ccd05 502 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 503 504 - const: zvfhmin 505 description: 506 The standard Zvfhmin extension for vectored minimal half-precision 507 floating-point instructions, as ratified in commit e2ccd05 508 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 509 510 - const: zvkb 511 description: 512 The standard Zvkb extension for vector cryptography bit-manipulation 513 instructions, as ratified in commit 56ed795 ("Update 514 riscv-crypto-spec-vector.adoc") of riscv-crypto. 515 516 - const: zvkg 517 description: 518 The standard Zvkg extension for vector GCM/GMAC instructions, as 519 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 520 of riscv-crypto. 521 522 - const: zvkn 523 description: 524 The standard Zvkn extension for NIST algorithm suite instructions, as 525 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 526 of riscv-crypto. 527 528 - const: zvknc 529 description: 530 The standard Zvknc extension for NIST algorithm suite with carryless 531 multiply instructions, as ratified in commit 56ed795 ("Update 532 riscv-crypto-spec-vector.adoc") of riscv-crypto. 533 534 - const: zvkned 535 description: 536 The standard Zvkned extension for Vector AES block cipher 537 instructions, as ratified in commit 56ed795 ("Update 538 riscv-crypto-spec-vector.adoc") of riscv-crypto. 539 540 - const: zvkng 541 description: 542 The standard Zvkng extension for NIST algorithm suite with GCM 543 instructions, as ratified in commit 56ed795 ("Update 544 riscv-crypto-spec-vector.adoc") of riscv-crypto. 545 546 - const: zvknha 547 description: | 548 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 549 hash (SHA-256 only) instructions, as ratified in commit 550 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 551 552 - const: zvknhb 553 description: | 554 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 555 hash (SHA-256 and SHA-512) instructions, as ratified in commit 556 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 557 558 - const: zvks 559 description: 560 The standard Zvks extension for ShangMi algorithm suite 561 instructions, as ratified in commit 56ed795 ("Update 562 riscv-crypto-spec-vector.adoc") of riscv-crypto. 563 564 - const: zvksc 565 description: 566 The standard Zvksc extension for ShangMi algorithm suite with 567 carryless multiplication instructions, as ratified in commit 56ed795 568 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 569 570 - const: zvksed 571 description: | 572 The standard Zvksed extension for ShangMi suite: SM4 block cipher 573 instructions, as ratified in commit 56ed795 ("Update 574 riscv-crypto-spec-vector.adoc") of riscv-crypto. 575 576 - const: zvksh 577 description: | 578 The standard Zvksh extension for ShangMi suite: SM3 secure hash 579 instructions, as ratified in commit 56ed795 ("Update 580 riscv-crypto-spec-vector.adoc") of riscv-crypto. 581 582 - const: zvksg 583 description: 584 The standard Zvksg extension for ShangMi algorithm suite with GCM 585 instructions, as ratified in commit 56ed795 ("Update 586 riscv-crypto-spec-vector.adoc") of riscv-crypto. 587 588 - const: zvkt 589 description: 590 The standard Zvkt extension for vector data-independent execution 591 latency, as ratified in commit 56ed795 ("Update 592 riscv-crypto-spec-vector.adoc") of riscv-crypto. 593 594 - const: xandespmu 595 description: 596 The Andes Technology performance monitor extension for counter overflow 597 and privilege mode filtering. For more details, see Counter Related 598 Registers in the AX45MP datasheet. 599 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 600 601 allOf: 602 # Zcb depends on Zca 603 - if: 604 contains: 605 const: zcb 606 then: 607 contains: 608 const: zca 609 # Zcd depends on Zca and D 610 - if: 611 contains: 612 const: zcd 613 then: 614 allOf: 615 - contains: 616 const: zca 617 - contains: 618 const: d 619 # Zcf depends on Zca and F 620 - if: 621 contains: 622 const: zcf 623 then: 624 allOf: 625 - contains: 626 const: zca 627 - contains: 628 const: f 629 # Zcmop depends on Zca 630 - if: 631 contains: 632 const: zcmop 633 then: 634 contains: 635 const: zca 636 637allOf: 638 # Zcf extension does not exist on rv64 639 - if: 640 properties: 641 riscv,isa-extensions: 642 contains: 643 const: zcf 644 riscv,isa-base: 645 contains: 646 const: rv64i 647 then: 648 properties: 649 riscv,isa-extensions: 650 not: 651 contains: 652 const: zcf 653 654additionalProperties: true 655... 656