1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27select: 28 properties: 29 compatible: 30 contains: 31 const: riscv 32 33properties: 34 riscv,isa: 35 description: 36 Identifies the specific RISC-V instruction set architecture 37 supported by the hart. These are documented in the RISC-V 38 User-Level ISA document, available from 39 https://riscv.org/specifications/ 40 41 Due to revisions of the ISA specification, some deviations 42 have arisen over time. 43 Notably, riscv,isa was defined prior to the creation of the 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45 implies "zicntr_zicsr_zifencei_zihpm". 46 47 While the isa strings in ISA specification are case 48 insensitive, letters in the riscv,isa string must be all 49 lowercase. 50 $ref: /schemas/types.yaml#/definitions/string 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 52 deprecated: true 53 54 riscv,isa-base: 55 description: 56 The base ISA implemented by this hart, as described by the 20191213 57 version of the unprivileged ISA specification. 58 enum: 59 - rv32i 60 - rv64i 61 62 riscv,isa-extensions: 63 $ref: /schemas/types.yaml#/definitions/string-array 64 minItems: 1 65 description: Extensions supported by the hart. 66 items: 67 anyOf: 68 # single letter extensions, in canonical order 69 - const: i 70 description: | 71 The base integer instruction set, as ratified in the 20191213 72 version of the unprivileged ISA specification. 73 74 This does not include Chapter 10, "Counters", which was moved into 75 the Zicntr and Zihpm extensions after the ratification of the 76 20191213 version of the unprivileged specification. 77 78 - const: m 79 description: 80 The standard M extension for integer multiplication and division, as 81 ratified in the 20191213 version of the unprivileged ISA 82 specification. 83 84 - const: a 85 description: 86 The standard A extension for atomic instructions, as ratified in the 87 20191213 version of the unprivileged ISA specification. 88 89 - const: f 90 description: 91 The standard F extension for single-precision floating point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: d 96 description: 97 The standard D extension for double-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: q 102 description: 103 The standard Q extension for quad-precision floating-point, as 104 ratified in the 20191213 version of the unprivileged ISA 105 specification. 106 107 - const: c 108 description: 109 The standard C extension for compressed instructions, as ratified in 110 the 20191213 version of the unprivileged ISA specification. 111 112 - const: v 113 description: 114 The standard V extension for vector operations, as ratified 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116 encoding") of the riscv-v-spec. 117 118 - const: h 119 description: 120 The standard H extension for hypervisors as ratified in the 20191213 121 version of the privileged ISA specification. 122 123 # multi-letter extensions, sorted alphanumerically 124 - const: smaia 125 description: | 126 The standard Smaia supervisor-level extension for the advanced 127 interrupt architecture for machine-mode-visible csr and behavioural 128 changes to interrupts as frozen at commit ccbddab ("Merge pull 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130 131 - const: smmpm 132 description: | 133 The standard Smmpm extension for M-mode pointer masking as 134 ratified at commit d70011dde6c2 ("Update to ratified state") 135 of riscv-j-extension. 136 137 - const: smnpm 138 description: | 139 The standard Smnpm extension for next-mode pointer masking as 140 ratified at commit d70011dde6c2 ("Update to ratified state") 141 of riscv-j-extension. 142 143 - const: smstateen 144 description: | 145 The standard Smstateen extension for controlling access to CSRs 146 added by other RISC-V extensions in H/S/VS/U/VU modes and as 147 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 148 149 - const: ssaia 150 description: | 151 The standard Ssaia supervisor-level extension for the advanced 152 interrupt architecture for supervisor-mode-visible csr and 153 behavioural changes to interrupts as frozen at commit ccbddab 154 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 155 156 - const: sscofpmf 157 description: | 158 The standard Sscofpmf supervisor-level extension for count overflow 159 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 160 to manually trigger workflow. (#2)") of riscv-count-overflow. 161 162 - const: ssnpm 163 description: | 164 The standard Ssnpm extension for next-mode pointer masking as 165 ratified at commit d70011dde6c2 ("Update to ratified state") 166 of riscv-j-extension. 167 168 - const: sstc 169 description: | 170 The standard Sstc supervisor-level extension for time compare as 171 ratified at commit 3f9ed34 ("Add ability to manually trigger 172 workflow. (#2)") of riscv-time-compare. 173 174 - const: svade 175 description: | 176 The standard Svade supervisor-level extension for SW-managed PTE A/D 177 bit updates as ratified in the 20240213 version of the privileged 178 ISA specification. 179 180 Both Svade and Svadu extensions control the hardware behavior when 181 the PTE A/D bits need to be set. The default behavior for the four 182 possible combinations of these extensions in the device tree are: 183 1) Neither Svade nor Svadu present in DT => It is technically 184 unknown whether the platform uses Svade or Svadu. Supervisor 185 software should be prepared to handle either hardware updating 186 of the PTE A/D bits or page faults when they need updated. 187 2) Only Svade present in DT => Supervisor must assume Svade to be 188 always enabled. 189 3) Only Svadu present in DT => Supervisor must assume Svadu to be 190 always enabled. 191 4) Both Svade and Svadu present in DT => Supervisor must assume 192 Svadu turned-off at boot time. To use Svadu, supervisor must 193 explicitly enable it using the SBI FWFT extension. 194 195 - const: svadu 196 description: | 197 The standard Svadu supervisor-level extension for hardware updating 198 of PTE A/D bits as ratified in the 20240528 version of the 199 privileged ISA specification. Please refer to Svade dt-binding 200 description for more details. 201 202 - const: svinval 203 description: 204 The standard Svinval supervisor-level extension for fine-grained 205 address-translation cache invalidation as ratified in the 20191213 206 version of the privileged ISA specification. 207 208 - const: svnapot 209 description: 210 The standard Svnapot supervisor-level extensions for napot 211 translation contiguity as ratified in the 20191213 version of the 212 privileged ISA specification. 213 214 - const: svpbmt 215 description: 216 The standard Svpbmt supervisor-level extensions for page-based 217 memory types as ratified in the 20191213 version of the privileged 218 ISA specification. 219 220 - const: svvptc 221 description: 222 The standard Svvptc supervisor-level extension for 223 address-translation cache behaviour with respect to invalid entries 224 as ratified at commit 4a69197e5617 ("Update to ratified state") of 225 riscv-svvptc. 226 227 - const: zabha 228 description: | 229 The Zabha extension for Byte and Halfword Atomic Memory Operations 230 as ratified at commit 49f49c842ff9 ("Update to Rafified state") of 231 riscv-zabha. 232 233 - const: zacas 234 description: | 235 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 236 is supported as ratified at commit 5059e0ca641c ("update to 237 ratified") of the riscv-zacas. 238 239 - const: zawrs 240 description: | 241 The Zawrs extension for entering a low-power state or for trapping 242 to a hypervisor while waiting on a store to a memory location, as 243 ratified in commit 98918c844281 ("Merge pull request #1217 from 244 riscv/zawrs") of riscv-isa-manual. 245 246 - const: zba 247 description: | 248 The standard Zba bit-manipulation extension for address generation 249 acceleration instructions as ratified at commit 6d33919 ("Merge pull 250 request #158 from hirooih/clmul-fix-loop-end-condition") of 251 riscv-bitmanip. 252 253 - const: zbb 254 description: | 255 The standard Zbb bit-manipulation extension for basic bit-manipulation 256 as ratified at commit 6d33919 ("Merge pull request #158 from 257 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 258 259 - const: zbc 260 description: | 261 The standard Zbc bit-manipulation extension for carry-less 262 multiplication as ratified at commit 6d33919 ("Merge pull request 263 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 264 265 - const: zbkb 266 description: 267 The standard Zbkb bitmanip instructions for cryptography as ratified 268 in version 1.0 of RISC-V Cryptography Extensions Volume I 269 specification. 270 271 - const: zbkc 272 description: 273 The standard Zbkc carry-less multiply instructions as ratified 274 in version 1.0 of RISC-V Cryptography Extensions Volume I 275 specification. 276 277 - const: zbkx 278 description: 279 The standard Zbkx crossbar permutation instructions as ratified 280 in version 1.0 of RISC-V Cryptography Extensions Volume I 281 specification. 282 283 - const: zbs 284 description: | 285 The standard Zbs bit-manipulation extension for single-bit 286 instructions as ratified at commit 6d33919 ("Merge pull request #158 287 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 288 289 - const: zca 290 description: | 291 The Zca extension part of Zc* standard extensions for code size 292 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 293 RV64 as it contains no instructions") of riscv-code-size-reduction, 294 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 295 of zc.adoc to src tree."). 296 297 - const: zcb 298 description: | 299 The Zcb extension part of Zc* standard extensions for code size 300 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 301 RV64 as it contains no instructions") of riscv-code-size-reduction, 302 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 303 of zc.adoc to src tree."). 304 305 - const: zcd 306 description: | 307 The Zcd extension part of Zc* standard extensions for code size 308 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 309 RV64 as it contains no instructions") of riscv-code-size-reduction, 310 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 311 of zc.adoc to src tree."). 312 313 - const: zcf 314 description: | 315 The Zcf extension part of Zc* standard extensions for code size 316 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 317 RV64 as it contains no instructions") of riscv-code-size-reduction, 318 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 319 of zc.adoc to src tree."). 320 321 - const: zcmop 322 description: 323 The standard Zcmop extension version 1.0, as ratified in commit 324 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 325 326 - const: zfa 327 description: 328 The standard Zfa extension for additional floating point 329 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 330 riscv-isa-manual. 331 332 - const: zfh 333 description: 334 The standard Zfh extension for 16-bit half-precision binary 335 floating-point instructions, as ratified in commit 64074bc ("Update 336 version numbers for Zfh/Zfinx") of riscv-isa-manual. 337 338 - const: zfhmin 339 description: 340 The standard Zfhmin extension which provides minimal support for 341 16-bit half-precision binary floating-point instructions, as ratified 342 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 343 riscv-isa-manual. 344 345 - const: ziccrse 346 description: 347 The standard Ziccrse extension which provides forward progress 348 guarantee on LR/SC sequences, as ratified in commit b1d806605f87 349 ("Updated to ratified state.") of the riscv profiles specification. 350 351 - const: zk 352 description: 353 The standard Zk Standard Scalar cryptography extension as ratified 354 in version 1.0 of RISC-V Cryptography Extensions Volume I 355 specification. 356 357 - const: zkn 358 description: 359 The standard Zkn NIST algorithm suite extensions as ratified in 360 version 1.0 of RISC-V Cryptography Extensions Volume I 361 specification. 362 363 - const: zknd 364 description: | 365 The standard Zknd for NIST suite: AES decryption instructions as 366 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 367 specification. 368 369 - const: zkne 370 description: | 371 The standard Zkne for NIST suite: AES encryption instructions as 372 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 373 specification. 374 375 - const: zknh 376 description: | 377 The standard Zknh for NIST suite: hash function instructions as 378 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 379 specification. 380 381 - const: zkr 382 description: 383 The standard Zkr entropy source extension as ratified in version 384 1.0 of RISC-V Cryptography Extensions Volume I specification. 385 This string being present means that the CSR associated to this 386 extension is accessible at the privilege level to which that 387 device-tree has been provided. 388 389 - const: zks 390 description: 391 The standard Zks ShangMi algorithm suite extensions as ratified in 392 version 1.0 of RISC-V Cryptography Extensions Volume I 393 specification. 394 395 - const: zksed 396 description: | 397 The standard Zksed for ShangMi suite: SM4 block cipher instructions 398 as ratified in version 1.0 of RISC-V Cryptography Extensions 399 Volume I specification. 400 401 - const: zksh 402 description: | 403 The standard Zksh for ShangMi suite: SM3 hash function instructions 404 as ratified in version 1.0 of RISC-V Cryptography Extensions 405 Volume I specification. 406 407 - const: zkt 408 description: 409 The standard Zkt for data independent execution latency as ratified 410 in version 1.0 of RISC-V Cryptography Extensions Volume I 411 specification. 412 413 - const: zicbom 414 description: 415 The standard Zicbom extension for base cache management operations as 416 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 417 418 - const: zicbop 419 description: 420 The standard Zicbop extension for cache-block prefetch instructions 421 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 422 riscv-CMOs. 423 424 - const: zicboz 425 description: 426 The standard Zicboz extension for cache-block zeroing as ratified 427 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 428 429 - const: zicntr 430 description: 431 The standard Zicntr extension for base counters and timers, as 432 ratified in the 20191213 version of the unprivileged ISA 433 specification. 434 435 - const: zicond 436 description: 437 The standard Zicond extension for conditional arithmetic and 438 conditional-select/move operations as ratified in commit 95cf1f9 439 ("Add changes requested by Ved during signoff") of riscv-zicond. 440 441 - const: zicsr 442 description: | 443 The standard Zicsr extension for control and status register 444 instructions, as ratified in the 20191213 version of the 445 unprivileged ISA specification. 446 447 This does not include Chapter 10, "Counters", which documents 448 special case read-only CSRs, that were moved into the Zicntr and 449 Zihpm extensions after the ratification of the 20191213 version of 450 the unprivileged specification. 451 452 - const: zifencei 453 description: 454 The standard Zifencei extension for instruction-fetch fence, as 455 ratified in the 20191213 version of the unprivileged ISA 456 specification. 457 458 - const: zihintpause 459 description: 460 The standard Zihintpause extension for pause hints, as ratified in 461 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 462 463 - const: zihintntl 464 description: 465 The standard Zihintntl extension for non-temporal locality hints, as 466 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 467 riscv-isa-manual. 468 469 - const: zihpm 470 description: 471 The standard Zihpm extension for hardware performance counters, as 472 ratified in the 20191213 version of the unprivileged ISA 473 specification. 474 475 - const: zimop 476 description: 477 The standard Zimop extension version 1.0, as ratified in commit 478 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 479 480 - const: ztso 481 description: 482 The standard Ztso extension for total store ordering, as ratified 483 in commit 2e5236 ("Ztso is now ratified.") of the 484 riscv-isa-manual. 485 486 - const: zvbb 487 description: 488 The standard Zvbb extension for vectored basic bit-manipulation 489 instructions, as ratified in commit 56ed795 ("Update 490 riscv-crypto-spec-vector.adoc") of riscv-crypto. 491 492 - const: zvbc 493 description: 494 The standard Zvbc extension for vectored carryless multiplication 495 instructions, as ratified in commit 56ed795 ("Update 496 riscv-crypto-spec-vector.adoc") of riscv-crypto. 497 498 - const: zve32f 499 description: 500 The standard Zve32f extension for embedded processors, as ratified 501 in commit 6f702a2 ("Vector extensions are now ratified") of 502 riscv-v-spec. 503 504 - const: zve32x 505 description: 506 The standard Zve32x extension for embedded processors, as ratified 507 in commit 6f702a2 ("Vector extensions are now ratified") of 508 riscv-v-spec. 509 510 - const: zve64d 511 description: 512 The standard Zve64d extension for embedded processors, as ratified 513 in commit 6f702a2 ("Vector extensions are now ratified") of 514 riscv-v-spec. 515 516 - const: zve64f 517 description: 518 The standard Zve64f extension for embedded processors, as ratified 519 in commit 6f702a2 ("Vector extensions are now ratified") of 520 riscv-v-spec. 521 522 - const: zve64x 523 description: 524 The standard Zve64x extension for embedded processors, as ratified 525 in commit 6f702a2 ("Vector extensions are now ratified") of 526 riscv-v-spec. 527 528 - const: zvfh 529 description: 530 The standard Zvfh extension for vectored half-precision 531 floating-point instructions, as ratified in commit e2ccd05 532 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 533 534 - const: zvfhmin 535 description: 536 The standard Zvfhmin extension for vectored minimal half-precision 537 floating-point instructions, as ratified in commit e2ccd05 538 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 539 540 - const: zvkb 541 description: 542 The standard Zvkb extension for vector cryptography bit-manipulation 543 instructions, as ratified in commit 56ed795 ("Update 544 riscv-crypto-spec-vector.adoc") of riscv-crypto. 545 546 - const: zvkg 547 description: 548 The standard Zvkg extension for vector GCM/GMAC instructions, as 549 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 550 of riscv-crypto. 551 552 - const: zvkn 553 description: 554 The standard Zvkn extension for NIST algorithm suite instructions, as 555 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 556 of riscv-crypto. 557 558 - const: zvknc 559 description: 560 The standard Zvknc extension for NIST algorithm suite with carryless 561 multiply instructions, as ratified in commit 56ed795 ("Update 562 riscv-crypto-spec-vector.adoc") of riscv-crypto. 563 564 - const: zvkned 565 description: 566 The standard Zvkned extension for Vector AES block cipher 567 instructions, as ratified in commit 56ed795 ("Update 568 riscv-crypto-spec-vector.adoc") of riscv-crypto. 569 570 - const: zvkng 571 description: 572 The standard Zvkng extension for NIST algorithm suite with GCM 573 instructions, as ratified in commit 56ed795 ("Update 574 riscv-crypto-spec-vector.adoc") of riscv-crypto. 575 576 - const: zvknha 577 description: | 578 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 579 hash (SHA-256 only) instructions, as ratified in commit 580 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 581 582 - const: zvknhb 583 description: | 584 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 585 hash (SHA-256 and SHA-512) instructions, as ratified in commit 586 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 587 588 - const: zvks 589 description: 590 The standard Zvks extension for ShangMi algorithm suite 591 instructions, as ratified in commit 56ed795 ("Update 592 riscv-crypto-spec-vector.adoc") of riscv-crypto. 593 594 - const: zvksc 595 description: 596 The standard Zvksc extension for ShangMi algorithm suite with 597 carryless multiplication instructions, as ratified in commit 56ed795 598 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 599 600 - const: zvksed 601 description: | 602 The standard Zvksed extension for ShangMi suite: SM4 block cipher 603 instructions, as ratified in commit 56ed795 ("Update 604 riscv-crypto-spec-vector.adoc") of riscv-crypto. 605 606 - const: zvksh 607 description: | 608 The standard Zvksh extension for ShangMi suite: SM3 secure hash 609 instructions, as ratified in commit 56ed795 ("Update 610 riscv-crypto-spec-vector.adoc") of riscv-crypto. 611 612 - const: zvksg 613 description: 614 The standard Zvksg extension for ShangMi algorithm suite with GCM 615 instructions, as ratified in commit 56ed795 ("Update 616 riscv-crypto-spec-vector.adoc") of riscv-crypto. 617 618 - const: zvkt 619 description: 620 The standard Zvkt extension for vector data-independent execution 621 latency, as ratified in commit 56ed795 ("Update 622 riscv-crypto-spec-vector.adoc") of riscv-crypto. 623 624 - const: xandespmu 625 description: 626 The Andes Technology performance monitor extension for counter overflow 627 and privilege mode filtering. For more details, see Counter Related 628 Registers in the AX45MP datasheet. 629 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 630 631 allOf: 632 # Zcb depends on Zca 633 - if: 634 contains: 635 const: zcb 636 then: 637 contains: 638 const: zca 639 # Zcd depends on Zca and D 640 - if: 641 contains: 642 const: zcd 643 then: 644 allOf: 645 - contains: 646 const: zca 647 - contains: 648 const: d 649 # Zcf depends on Zca and F 650 - if: 651 contains: 652 const: zcf 653 then: 654 allOf: 655 - contains: 656 const: zca 657 - contains: 658 const: f 659 # Zcmop depends on Zca 660 - if: 661 contains: 662 const: zcmop 663 then: 664 contains: 665 const: zca 666 667allOf: 668 # Zcf extension does not exist on rv64 669 - if: 670 properties: 671 riscv,isa-extensions: 672 contains: 673 const: zcf 674 riscv,isa-base: 675 contains: 676 const: rv64i 677 then: 678 properties: 679 riscv,isa-extensions: 680 not: 681 contains: 682 const: zcf 683 684additionalProperties: true 685... 686