1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27select: 28 properties: 29 compatible: 30 contains: 31 const: riscv 32 33properties: 34 riscv,isa: 35 description: 36 Identifies the specific RISC-V instruction set architecture 37 supported by the hart. These are documented in the RISC-V 38 User-Level ISA document, available from 39 https://riscv.org/specifications/ 40 41 Due to revisions of the ISA specification, some deviations 42 have arisen over time. 43 Notably, riscv,isa was defined prior to the creation of the 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45 implies "zicntr_zicsr_zifencei_zihpm". 46 47 While the isa strings in ISA specification are case 48 insensitive, letters in the riscv,isa string must be all 49 lowercase. 50 $ref: /schemas/types.yaml#/definitions/string 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 52 deprecated: true 53 54 riscv,isa-base: 55 description: 56 The base ISA implemented by this hart, as described by the 20191213 57 version of the unprivileged ISA specification. 58 enum: 59 - rv32i 60 - rv64i 61 62 riscv,isa-extensions: 63 $ref: /schemas/types.yaml#/definitions/string-array 64 minItems: 1 65 description: Extensions supported by the hart. 66 items: 67 anyOf: 68 # single letter extensions, in canonical order 69 - const: i 70 description: | 71 The base integer instruction set, as ratified in the 20191213 72 version of the unprivileged ISA specification. 73 74 This does not include Chapter 10, "Counters", which was moved into 75 the Zicntr and Zihpm extensions after the ratification of the 76 20191213 version of the unprivileged specification. 77 78 - const: m 79 description: 80 The standard M extension for integer multiplication and division, as 81 ratified in the 20191213 version of the unprivileged ISA 82 specification. 83 84 - const: a 85 description: 86 The standard A extension for atomic instructions, as ratified in the 87 20191213 version of the unprivileged ISA specification. 88 89 - const: f 90 description: 91 The standard F extension for single-precision floating point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: d 96 description: 97 The standard D extension for double-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: q 102 description: 103 The standard Q extension for quad-precision floating-point, as 104 ratified in the 20191213 version of the unprivileged ISA 105 specification. 106 107 - const: c 108 description: 109 The standard C extension for compressed instructions, as ratified in 110 the 20191213 version of the unprivileged ISA specification. 111 112 - const: v 113 description: 114 The standard V extension for vector operations, as ratified 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116 encoding") of the riscv-v-spec. 117 118 - const: h 119 description: 120 The standard H extension for hypervisors as ratified in the 20191213 121 version of the privileged ISA specification. 122 123 # multi-letter extensions, sorted alphanumerically 124 - const: smaia 125 description: | 126 The standard Smaia supervisor-level extension for the advanced 127 interrupt architecture for machine-mode-visible csr and behavioural 128 changes to interrupts as frozen at commit ccbddab ("Merge pull 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130 131 - const: smstateen 132 description: | 133 The standard Smstateen extension for controlling access to CSRs 134 added by other RISC-V extensions in H/S/VS/U/VU modes and as 135 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 136 137 - const: ssaia 138 description: | 139 The standard Ssaia supervisor-level extension for the advanced 140 interrupt architecture for supervisor-mode-visible csr and 141 behavioural changes to interrupts as frozen at commit ccbddab 142 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 143 144 - const: sscofpmf 145 description: | 146 The standard Sscofpmf supervisor-level extension for count overflow 147 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 148 to manually trigger workflow. (#2)") of riscv-count-overflow. 149 150 - const: sstc 151 description: | 152 The standard Sstc supervisor-level extension for time compare as 153 ratified at commit 3f9ed34 ("Add ability to manually trigger 154 workflow. (#2)") of riscv-time-compare. 155 156 - const: svinval 157 description: 158 The standard Svinval supervisor-level extension for fine-grained 159 address-translation cache invalidation as ratified in the 20191213 160 version of the privileged ISA specification. 161 162 - const: svnapot 163 description: 164 The standard Svnapot supervisor-level extensions for napot 165 translation contiguity as ratified in the 20191213 version of the 166 privileged ISA specification. 167 168 - const: svpbmt 169 description: 170 The standard Svpbmt supervisor-level extensions for page-based 171 memory types as ratified in the 20191213 version of the privileged 172 ISA specification. 173 174 - const: zacas 175 description: | 176 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 177 is supported as ratified at commit 5059e0ca641c ("update to 178 ratified") of the riscv-zacas. 179 180 - const: zba 181 description: | 182 The standard Zba bit-manipulation extension for address generation 183 acceleration instructions as ratified at commit 6d33919 ("Merge pull 184 request #158 from hirooih/clmul-fix-loop-end-condition") of 185 riscv-bitmanip. 186 187 - const: zbb 188 description: | 189 The standard Zbb bit-manipulation extension for basic bit-manipulation 190 as ratified at commit 6d33919 ("Merge pull request #158 from 191 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 192 193 - const: zbc 194 description: | 195 The standard Zbc bit-manipulation extension for carry-less 196 multiplication as ratified at commit 6d33919 ("Merge pull request 197 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 198 199 - const: zbkb 200 description: 201 The standard Zbkb bitmanip instructions for cryptography as ratified 202 in version 1.0 of RISC-V Cryptography Extensions Volume I 203 specification. 204 205 - const: zbkc 206 description: 207 The standard Zbkc carry-less multiply instructions as ratified 208 in version 1.0 of RISC-V Cryptography Extensions Volume I 209 specification. 210 211 - const: zbkx 212 description: 213 The standard Zbkx crossbar permutation instructions as ratified 214 in version 1.0 of RISC-V Cryptography Extensions Volume I 215 specification. 216 217 - const: zbs 218 description: | 219 The standard Zbs bit-manipulation extension for single-bit 220 instructions as ratified at commit 6d33919 ("Merge pull request #158 221 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 222 223 - const: zfa 224 description: 225 The standard Zfa extension for additional floating point 226 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 227 riscv-isa-manual. 228 229 - const: zfh 230 description: 231 The standard Zfh extension for 16-bit half-precision binary 232 floating-point instructions, as ratified in commit 64074bc ("Update 233 version numbers for Zfh/Zfinx") of riscv-isa-manual. 234 235 - const: zfhmin 236 description: 237 The standard Zfhmin extension which provides minimal support for 238 16-bit half-precision binary floating-point instructions, as ratified 239 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 240 riscv-isa-manual. 241 242 - const: zk 243 description: 244 The standard Zk Standard Scalar cryptography extension as ratified 245 in version 1.0 of RISC-V Cryptography Extensions Volume I 246 specification. 247 248 - const: zkn 249 description: 250 The standard Zkn NIST algorithm suite extensions as ratified in 251 version 1.0 of RISC-V Cryptography Extensions Volume I 252 specification. 253 254 - const: zknd 255 description: | 256 The standard Zknd for NIST suite: AES decryption instructions as 257 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 258 specification. 259 260 - const: zkne 261 description: | 262 The standard Zkne for NIST suite: AES encryption instructions as 263 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 264 specification. 265 266 - const: zknh 267 description: | 268 The standard Zknh for NIST suite: hash function instructions as 269 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 270 specification. 271 272 - const: zkr 273 description: 274 The standard Zkr entropy source extension as ratified in version 275 1.0 of RISC-V Cryptography Extensions Volume I specification. 276 This string being present means that the CSR associated to this 277 extension is accessible at the privilege level to which that 278 device-tree has been provided. 279 280 - const: zks 281 description: 282 The standard Zks ShangMi algorithm suite extensions as ratified in 283 version 1.0 of RISC-V Cryptography Extensions Volume I 284 specification. 285 286 - const: zksed 287 description: | 288 The standard Zksed for ShangMi suite: SM4 block cipher instructions 289 as ratified in version 1.0 of RISC-V Cryptography Extensions 290 Volume I specification. 291 292 - const: zksh 293 description: | 294 The standard Zksh for ShangMi suite: SM3 hash function instructions 295 as ratified in version 1.0 of RISC-V Cryptography Extensions 296 Volume I specification. 297 298 - const: zkt 299 description: 300 The standard Zkt for data independent execution latency as ratified 301 in version 1.0 of RISC-V Cryptography Extensions Volume I 302 specification. 303 304 - const: zicbom 305 description: 306 The standard Zicbom extension for base cache management operations as 307 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 308 309 - const: zicbop 310 description: 311 The standard Zicbop extension for cache-block prefetch instructions 312 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 313 riscv-CMOs. 314 315 - const: zicboz 316 description: 317 The standard Zicboz extension for cache-block zeroing as ratified 318 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 319 320 - const: zicntr 321 description: 322 The standard Zicntr extension for base counters and timers, as 323 ratified in the 20191213 version of the unprivileged ISA 324 specification. 325 326 - const: zicond 327 description: 328 The standard Zicond extension for conditional arithmetic and 329 conditional-select/move operations as ratified in commit 95cf1f9 330 ("Add changes requested by Ved during signoff") of riscv-zicond. 331 332 - const: zicsr 333 description: | 334 The standard Zicsr extension for control and status register 335 instructions, as ratified in the 20191213 version of the 336 unprivileged ISA specification. 337 338 This does not include Chapter 10, "Counters", which documents 339 special case read-only CSRs, that were moved into the Zicntr and 340 Zihpm extensions after the ratification of the 20191213 version of 341 the unprivileged specification. 342 343 - const: zifencei 344 description: 345 The standard Zifencei extension for instruction-fetch fence, as 346 ratified in the 20191213 version of the unprivileged ISA 347 specification. 348 349 - const: zihintpause 350 description: 351 The standard Zihintpause extension for pause hints, as ratified in 352 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 353 354 - const: zihintntl 355 description: 356 The standard Zihintntl extension for non-temporal locality hints, as 357 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 358 riscv-isa-manual. 359 360 - const: zihpm 361 description: 362 The standard Zihpm extension for hardware performance counters, as 363 ratified in the 20191213 version of the unprivileged ISA 364 specification. 365 366 - const: ztso 367 description: 368 The standard Ztso extension for total store ordering, as ratified 369 in commit 2e5236 ("Ztso is now ratified.") of the 370 riscv-isa-manual. 371 372 - const: zvbb 373 description: 374 The standard Zvbb extension for vectored basic bit-manipulation 375 instructions, as ratified in commit 56ed795 ("Update 376 riscv-crypto-spec-vector.adoc") of riscv-crypto. 377 378 - const: zvbc 379 description: 380 The standard Zvbc extension for vectored carryless multiplication 381 instructions, as ratified in commit 56ed795 ("Update 382 riscv-crypto-spec-vector.adoc") of riscv-crypto. 383 384 - const: zvfh 385 description: 386 The standard Zvfh extension for vectored half-precision 387 floating-point instructions, as ratified in commit e2ccd05 388 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 389 390 - const: zvfhmin 391 description: 392 The standard Zvfhmin extension for vectored minimal half-precision 393 floating-point instructions, as ratified in commit e2ccd05 394 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 395 396 - const: zvkb 397 description: 398 The standard Zvkb extension for vector cryptography bit-manipulation 399 instructions, as ratified in commit 56ed795 ("Update 400 riscv-crypto-spec-vector.adoc") of riscv-crypto. 401 402 - const: zvkg 403 description: 404 The standard Zvkg extension for vector GCM/GMAC instructions, as 405 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 406 of riscv-crypto. 407 408 - const: zvkn 409 description: 410 The standard Zvkn extension for NIST algorithm suite instructions, as 411 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 412 of riscv-crypto. 413 414 - const: zvknc 415 description: 416 The standard Zvknc extension for NIST algorithm suite with carryless 417 multiply instructions, as ratified in commit 56ed795 ("Update 418 riscv-crypto-spec-vector.adoc") of riscv-crypto. 419 420 - const: zvkned 421 description: 422 The standard Zvkned extension for Vector AES block cipher 423 instructions, as ratified in commit 56ed795 ("Update 424 riscv-crypto-spec-vector.adoc") of riscv-crypto. 425 426 - const: zvkng 427 description: 428 The standard Zvkng extension for NIST algorithm suite with GCM 429 instructions, as ratified in commit 56ed795 ("Update 430 riscv-crypto-spec-vector.adoc") of riscv-crypto. 431 432 - const: zvknha 433 description: | 434 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 435 hash (SHA-256 only) instructions, as ratified in commit 436 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 437 438 - const: zvknhb 439 description: | 440 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 441 hash (SHA-256 and SHA-512) instructions, as ratified in commit 442 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 443 444 - const: zvks 445 description: 446 The standard Zvks extension for ShangMi algorithm suite 447 instructions, as ratified in commit 56ed795 ("Update 448 riscv-crypto-spec-vector.adoc") of riscv-crypto. 449 450 - const: zvksc 451 description: 452 The standard Zvksc extension for ShangMi algorithm suite with 453 carryless multiplication instructions, as ratified in commit 56ed795 454 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 455 456 - const: zvksed 457 description: | 458 The standard Zvksed extension for ShangMi suite: SM4 block cipher 459 instructions, as ratified in commit 56ed795 ("Update 460 riscv-crypto-spec-vector.adoc") of riscv-crypto. 461 462 - const: zvksh 463 description: | 464 The standard Zvksh extension for ShangMi suite: SM3 secure hash 465 instructions, as ratified in commit 56ed795 ("Update 466 riscv-crypto-spec-vector.adoc") of riscv-crypto. 467 468 - const: zvksg 469 description: 470 The standard Zvksg extension for ShangMi algorithm suite with GCM 471 instructions, as ratified in commit 56ed795 ("Update 472 riscv-crypto-spec-vector.adoc") of riscv-crypto. 473 474 - const: zvkt 475 description: 476 The standard Zvkt extension for vector data-independent execution 477 latency, as ratified in commit 56ed795 ("Update 478 riscv-crypto-spec-vector.adoc") of riscv-crypto. 479 480 - const: xandespmu 481 description: 482 The Andes Technology performance monitor extension for counter overflow 483 and privilege mode filtering. For more details, see Counter Related 484 Registers in the AX45MP datasheet. 485 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 486 487additionalProperties: true 488... 489