1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27select: 28 properties: 29 compatible: 30 contains: 31 const: riscv 32 33properties: 34 riscv,isa: 35 description: 36 Identifies the specific RISC-V instruction set architecture 37 supported by the hart. These are documented in the RISC-V 38 User-Level ISA document, available from 39 https://riscv.org/specifications/ 40 41 Due to revisions of the ISA specification, some deviations 42 have arisen over time. 43 Notably, riscv,isa was defined prior to the creation of the 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45 implies "zicntr_zicsr_zifencei_zihpm". 46 47 While the isa strings in ISA specification are case 48 insensitive, letters in the riscv,isa string must be all 49 lowercase. 50 $ref: /schemas/types.yaml#/definitions/string 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 52 deprecated: true 53 54 riscv,isa-base: 55 description: 56 The base ISA implemented by this hart, as described by the 20191213 57 version of the unprivileged ISA specification. 58 enum: 59 - rv32i 60 - rv64i 61 62 riscv,isa-extensions: 63 $ref: /schemas/types.yaml#/definitions/string-array 64 minItems: 1 65 description: Extensions supported by the hart. 66 items: 67 anyOf: 68 # single letter extensions, in canonical order 69 - const: i 70 description: | 71 The base integer instruction set, as ratified in the 20191213 72 version of the unprivileged ISA specification. 73 74 This does not include Chapter 10, "Counters", which was moved into 75 the Zicntr and Zihpm extensions after the ratification of the 76 20191213 version of the unprivileged specification. 77 78 - const: m 79 description: 80 The standard M extension for integer multiplication and division, as 81 ratified in the 20191213 version of the unprivileged ISA 82 specification. 83 84 - const: a 85 description: 86 The standard A extension for atomic instructions, as ratified in the 87 20191213 version of the unprivileged ISA specification. 88 89 - const: f 90 description: 91 The standard F extension for single-precision floating point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: d 96 description: 97 The standard D extension for double-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: q 102 description: 103 The standard Q extension for quad-precision floating-point, as 104 ratified in the 20191213 version of the unprivileged ISA 105 specification. 106 107 - const: c 108 description: 109 The standard C extension for compressed instructions, as ratified in 110 the 20191213 version of the unprivileged ISA specification. 111 112 - const: v 113 description: 114 The standard V extension for vector operations, as ratified 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116 encoding") of the riscv-v-spec. 117 118 - const: h 119 description: 120 The standard H extension for hypervisors as ratified in the 20191213 121 version of the privileged ISA specification. 122 123 # multi-letter extensions, sorted alphanumerically 124 - const: smaia 125 description: | 126 The standard Smaia supervisor-level extension for the advanced 127 interrupt architecture for machine-mode-visible csr and behavioural 128 changes to interrupts as frozen at commit ccbddab ("Merge pull 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130 131 - const: smstateen 132 description: | 133 The standard Smstateen extension for controlling access to CSRs 134 added by other RISC-V extensions in H/S/VS/U/VU modes and as 135 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 136 137 - const: ssaia 138 description: | 139 The standard Ssaia supervisor-level extension for the advanced 140 interrupt architecture for supervisor-mode-visible csr and 141 behavioural changes to interrupts as frozen at commit ccbddab 142 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 143 144 - const: sscofpmf 145 description: | 146 The standard Sscofpmf supervisor-level extension for count overflow 147 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 148 to manually trigger workflow. (#2)") of riscv-count-overflow. 149 150 - const: sstc 151 description: | 152 The standard Sstc supervisor-level extension for time compare as 153 ratified at commit 3f9ed34 ("Add ability to manually trigger 154 workflow. (#2)") of riscv-time-compare. 155 156 - const: svinval 157 description: 158 The standard Svinval supervisor-level extension for fine-grained 159 address-translation cache invalidation as ratified in the 20191213 160 version of the privileged ISA specification. 161 162 - const: svnapot 163 description: 164 The standard Svnapot supervisor-level extensions for napot 165 translation contiguity as ratified in the 20191213 version of the 166 privileged ISA specification. 167 168 - const: svpbmt 169 description: 170 The standard Svpbmt supervisor-level extensions for page-based 171 memory types as ratified in the 20191213 version of the privileged 172 ISA specification. 173 174 - const: zacas 175 description: | 176 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 177 is supported as ratified at commit 5059e0ca641c ("update to 178 ratified") of the riscv-zacas. 179 180 - const: zawrs 181 description: | 182 The Zawrs extension for entering a low-power state or for trapping 183 to a hypervisor while waiting on a store to a memory location, as 184 ratified in commit 98918c844281 ("Merge pull request #1217 from 185 riscv/zawrs") of riscv-isa-manual. 186 187 - const: zba 188 description: | 189 The standard Zba bit-manipulation extension for address generation 190 acceleration instructions as ratified at commit 6d33919 ("Merge pull 191 request #158 from hirooih/clmul-fix-loop-end-condition") of 192 riscv-bitmanip. 193 194 - const: zbb 195 description: | 196 The standard Zbb bit-manipulation extension for basic bit-manipulation 197 as ratified at commit 6d33919 ("Merge pull request #158 from 198 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 199 200 - const: zbc 201 description: | 202 The standard Zbc bit-manipulation extension for carry-less 203 multiplication as ratified at commit 6d33919 ("Merge pull request 204 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 205 206 - const: zbkb 207 description: 208 The standard Zbkb bitmanip instructions for cryptography as ratified 209 in version 1.0 of RISC-V Cryptography Extensions Volume I 210 specification. 211 212 - const: zbkc 213 description: 214 The standard Zbkc carry-less multiply instructions as ratified 215 in version 1.0 of RISC-V Cryptography Extensions Volume I 216 specification. 217 218 - const: zbkx 219 description: 220 The standard Zbkx crossbar permutation instructions as ratified 221 in version 1.0 of RISC-V Cryptography Extensions Volume I 222 specification. 223 224 - const: zbs 225 description: | 226 The standard Zbs bit-manipulation extension for single-bit 227 instructions as ratified at commit 6d33919 ("Merge pull request #158 228 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 229 230 - const: zfa 231 description: 232 The standard Zfa extension for additional floating point 233 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 234 riscv-isa-manual. 235 236 - const: zfh 237 description: 238 The standard Zfh extension for 16-bit half-precision binary 239 floating-point instructions, as ratified in commit 64074bc ("Update 240 version numbers for Zfh/Zfinx") of riscv-isa-manual. 241 242 - const: zfhmin 243 description: 244 The standard Zfhmin extension which provides minimal support for 245 16-bit half-precision binary floating-point instructions, as ratified 246 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 247 riscv-isa-manual. 248 249 - const: zk 250 description: 251 The standard Zk Standard Scalar cryptography extension as ratified 252 in version 1.0 of RISC-V Cryptography Extensions Volume I 253 specification. 254 255 - const: zkn 256 description: 257 The standard Zkn NIST algorithm suite extensions as ratified in 258 version 1.0 of RISC-V Cryptography Extensions Volume I 259 specification. 260 261 - const: zknd 262 description: | 263 The standard Zknd for NIST suite: AES decryption instructions as 264 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 265 specification. 266 267 - const: zkne 268 description: | 269 The standard Zkne for NIST suite: AES encryption instructions as 270 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 271 specification. 272 273 - const: zknh 274 description: | 275 The standard Zknh for NIST suite: hash function instructions as 276 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 277 specification. 278 279 - const: zkr 280 description: 281 The standard Zkr entropy source extension as ratified in version 282 1.0 of RISC-V Cryptography Extensions Volume I specification. 283 This string being present means that the CSR associated to this 284 extension is accessible at the privilege level to which that 285 device-tree has been provided. 286 287 - const: zks 288 description: 289 The standard Zks ShangMi algorithm suite extensions as ratified in 290 version 1.0 of RISC-V Cryptography Extensions Volume I 291 specification. 292 293 - const: zksed 294 description: | 295 The standard Zksed for ShangMi suite: SM4 block cipher instructions 296 as ratified in version 1.0 of RISC-V Cryptography Extensions 297 Volume I specification. 298 299 - const: zksh 300 description: | 301 The standard Zksh for ShangMi suite: SM3 hash function instructions 302 as ratified in version 1.0 of RISC-V Cryptography Extensions 303 Volume I specification. 304 305 - const: zkt 306 description: 307 The standard Zkt for data independent execution latency as ratified 308 in version 1.0 of RISC-V Cryptography Extensions Volume I 309 specification. 310 311 - const: zicbom 312 description: 313 The standard Zicbom extension for base cache management operations as 314 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 315 316 - const: zicbop 317 description: 318 The standard Zicbop extension for cache-block prefetch instructions 319 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 320 riscv-CMOs. 321 322 - const: zicboz 323 description: 324 The standard Zicboz extension for cache-block zeroing as ratified 325 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 326 327 - const: zicntr 328 description: 329 The standard Zicntr extension for base counters and timers, as 330 ratified in the 20191213 version of the unprivileged ISA 331 specification. 332 333 - const: zicond 334 description: 335 The standard Zicond extension for conditional arithmetic and 336 conditional-select/move operations as ratified in commit 95cf1f9 337 ("Add changes requested by Ved during signoff") of riscv-zicond. 338 339 - const: zicsr 340 description: | 341 The standard Zicsr extension for control and status register 342 instructions, as ratified in the 20191213 version of the 343 unprivileged ISA specification. 344 345 This does not include Chapter 10, "Counters", which documents 346 special case read-only CSRs, that were moved into the Zicntr and 347 Zihpm extensions after the ratification of the 20191213 version of 348 the unprivileged specification. 349 350 - const: zifencei 351 description: 352 The standard Zifencei extension for instruction-fetch fence, as 353 ratified in the 20191213 version of the unprivileged ISA 354 specification. 355 356 - const: zihintpause 357 description: 358 The standard Zihintpause extension for pause hints, as ratified in 359 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 360 361 - const: zihintntl 362 description: 363 The standard Zihintntl extension for non-temporal locality hints, as 364 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 365 riscv-isa-manual. 366 367 - const: zihpm 368 description: 369 The standard Zihpm extension for hardware performance counters, as 370 ratified in the 20191213 version of the unprivileged ISA 371 specification. 372 373 - const: ztso 374 description: 375 The standard Ztso extension for total store ordering, as ratified 376 in commit 2e5236 ("Ztso is now ratified.") of the 377 riscv-isa-manual. 378 379 - const: zvbb 380 description: 381 The standard Zvbb extension for vectored basic bit-manipulation 382 instructions, as ratified in commit 56ed795 ("Update 383 riscv-crypto-spec-vector.adoc") of riscv-crypto. 384 385 - const: zvbc 386 description: 387 The standard Zvbc extension for vectored carryless multiplication 388 instructions, as ratified in commit 56ed795 ("Update 389 riscv-crypto-spec-vector.adoc") of riscv-crypto. 390 391 - const: zvfh 392 description: 393 The standard Zvfh extension for vectored half-precision 394 floating-point instructions, as ratified in commit e2ccd05 395 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 396 397 - const: zvfhmin 398 description: 399 The standard Zvfhmin extension for vectored minimal half-precision 400 floating-point instructions, as ratified in commit e2ccd05 401 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 402 403 - const: zvkb 404 description: 405 The standard Zvkb extension for vector cryptography bit-manipulation 406 instructions, as ratified in commit 56ed795 ("Update 407 riscv-crypto-spec-vector.adoc") of riscv-crypto. 408 409 - const: zvkg 410 description: 411 The standard Zvkg extension for vector GCM/GMAC instructions, as 412 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 413 of riscv-crypto. 414 415 - const: zvkn 416 description: 417 The standard Zvkn extension for NIST algorithm suite instructions, as 418 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 419 of riscv-crypto. 420 421 - const: zvknc 422 description: 423 The standard Zvknc extension for NIST algorithm suite with carryless 424 multiply instructions, as ratified in commit 56ed795 ("Update 425 riscv-crypto-spec-vector.adoc") of riscv-crypto. 426 427 - const: zvkned 428 description: 429 The standard Zvkned extension for Vector AES block cipher 430 instructions, as ratified in commit 56ed795 ("Update 431 riscv-crypto-spec-vector.adoc") of riscv-crypto. 432 433 - const: zvkng 434 description: 435 The standard Zvkng extension for NIST algorithm suite with GCM 436 instructions, as ratified in commit 56ed795 ("Update 437 riscv-crypto-spec-vector.adoc") of riscv-crypto. 438 439 - const: zvknha 440 description: | 441 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 442 hash (SHA-256 only) instructions, as ratified in commit 443 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 444 445 - const: zvknhb 446 description: | 447 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 448 hash (SHA-256 and SHA-512) instructions, as ratified in commit 449 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 450 451 - const: zvks 452 description: 453 The standard Zvks extension for ShangMi algorithm suite 454 instructions, as ratified in commit 56ed795 ("Update 455 riscv-crypto-spec-vector.adoc") of riscv-crypto. 456 457 - const: zvksc 458 description: 459 The standard Zvksc extension for ShangMi algorithm suite with 460 carryless multiplication instructions, as ratified in commit 56ed795 461 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 462 463 - const: zvksed 464 description: | 465 The standard Zvksed extension for ShangMi suite: SM4 block cipher 466 instructions, as ratified in commit 56ed795 ("Update 467 riscv-crypto-spec-vector.adoc") of riscv-crypto. 468 469 - const: zvksh 470 description: | 471 The standard Zvksh extension for ShangMi suite: SM3 secure hash 472 instructions, as ratified in commit 56ed795 ("Update 473 riscv-crypto-spec-vector.adoc") of riscv-crypto. 474 475 - const: zvksg 476 description: 477 The standard Zvksg extension for ShangMi algorithm suite with GCM 478 instructions, as ratified in commit 56ed795 ("Update 479 riscv-crypto-spec-vector.adoc") of riscv-crypto. 480 481 - const: zvkt 482 description: 483 The standard Zvkt extension for vector data-independent execution 484 latency, as ratified in commit 56ed795 ("Update 485 riscv-crypto-spec-vector.adoc") of riscv-crypto. 486 487 - const: xandespmu 488 description: 489 The Andes Technology performance monitor extension for counter overflow 490 and privilege mode filtering. For more details, see Counter Related 491 Registers in the AX45MP datasheet. 492 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 493 494additionalProperties: true 495... 496