1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27select: 28 properties: 29 compatible: 30 contains: 31 const: riscv 32 33properties: 34 riscv,isa: 35 description: 36 Identifies the specific RISC-V instruction set architecture 37 supported by the hart. These are documented in the RISC-V 38 User-Level ISA document, available from 39 https://riscv.org/specifications/ 40 41 Due to revisions of the ISA specification, some deviations 42 have arisen over time. 43 Notably, riscv,isa was defined prior to the creation of the 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45 implies "zicntr_zicsr_zifencei_zihpm". 46 47 While the isa strings in ISA specification are case 48 insensitive, letters in the riscv,isa string must be all 49 lowercase. 50 $ref: /schemas/types.yaml#/definitions/string 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ 52 deprecated: true 53 54 riscv,isa-base: 55 description: 56 The base ISA implemented by this hart, as described by the 20191213 57 version of the unprivileged ISA specification. 58 enum: 59 - rv32i 60 - rv64i 61 62 riscv,isa-extensions: 63 $ref: /schemas/types.yaml#/definitions/string-array 64 minItems: 1 65 description: Extensions supported by the hart. 66 items: 67 anyOf: 68 # single letter extensions, in canonical order 69 - const: i 70 description: | 71 The base integer instruction set, as ratified in the 20191213 72 version of the unprivileged ISA specification. 73 74 This does not include Chapter 10, "Counters", which was moved into 75 the Zicntr and Zihpm extensions after the ratification of the 76 20191213 version of the unprivileged specification. 77 78 - const: m 79 description: 80 The standard M extension for integer multiplication and division, as 81 ratified in the 20191213 version of the unprivileged ISA 82 specification. 83 84 - const: a 85 description: 86 The standard A extension for atomic instructions, as ratified in the 87 20191213 version of the unprivileged ISA specification. 88 89 - const: f 90 description: 91 The standard F extension for single-precision floating point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: d 96 description: 97 The standard D extension for double-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: q 102 description: 103 The standard Q extension for quad-precision floating-point, as 104 ratified in the 20191213 version of the unprivileged ISA 105 specification. 106 107 - const: c 108 description: 109 The standard C extension for compressed instructions, as ratified in 110 the 20191213 version of the unprivileged ISA specification. 111 112 - const: v 113 description: 114 The standard V extension for vector operations, as ratified 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116 encoding") of the riscv-v-spec. 117 118 - const: h 119 description: 120 The standard H extension for hypervisors as ratified in the 20191213 121 version of the privileged ISA specification. 122 123 # multi-letter extensions, sorted alphanumerically 124 - const: smaia 125 description: | 126 The standard Smaia supervisor-level extension for the advanced 127 interrupt architecture for machine-mode-visible csr and behavioural 128 changes to interrupts as frozen at commit ccbddab ("Merge pull 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130 131 - const: smstateen 132 description: | 133 The standard Smstateen extension for controlling access to CSRs 134 added by other RISC-V extensions in H/S/VS/U/VU modes and as 135 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 136 137 - const: ssaia 138 description: | 139 The standard Ssaia supervisor-level extension for the advanced 140 interrupt architecture for supervisor-mode-visible csr and 141 behavioural changes to interrupts as frozen at commit ccbddab 142 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 143 144 - const: sscofpmf 145 description: | 146 The standard Sscofpmf supervisor-level extension for count overflow 147 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 148 to manually trigger workflow. (#2)") of riscv-count-overflow. 149 150 - const: sstc 151 description: | 152 The standard Sstc supervisor-level extension for time compare as 153 ratified at commit 3f9ed34 ("Add ability to manually trigger 154 workflow. (#2)") of riscv-time-compare. 155 156 - const: svinval 157 description: 158 The standard Svinval supervisor-level extension for fine-grained 159 address-translation cache invalidation as ratified in the 20191213 160 version of the privileged ISA specification. 161 162 - const: svnapot 163 description: 164 The standard Svnapot supervisor-level extensions for napot 165 translation contiguity as ratified in the 20191213 version of the 166 privileged ISA specification. 167 168 - const: svpbmt 169 description: 170 The standard Svpbmt supervisor-level extensions for page-based 171 memory types as ratified in the 20191213 version of the privileged 172 ISA specification. 173 174 - const: zba 175 description: | 176 The standard Zba bit-manipulation extension for address generation 177 acceleration instructions as ratified at commit 6d33919 ("Merge pull 178 request #158 from hirooih/clmul-fix-loop-end-condition") of 179 riscv-bitmanip. 180 181 - const: zbb 182 description: | 183 The standard Zbb bit-manipulation extension for basic bit-manipulation 184 as ratified at commit 6d33919 ("Merge pull request #158 from 185 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 186 187 - const: zbc 188 description: | 189 The standard Zbc bit-manipulation extension for carry-less 190 multiplication as ratified at commit 6d33919 ("Merge pull request 191 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 192 193 - const: zbs 194 description: | 195 The standard Zbs bit-manipulation extension for single-bit 196 instructions as ratified at commit 6d33919 ("Merge pull request #158 197 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 198 199 - const: zicbom 200 description: 201 The standard Zicbom extension for base cache management operations as 202 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 203 204 - const: zicbop 205 description: 206 The standard Zicbop extension for cache-block prefetch instructions 207 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 208 riscv-CMOs. 209 210 - const: zicboz 211 description: 212 The standard Zicboz extension for cache-block zeroing as ratified 213 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 214 215 - const: zicntr 216 description: 217 The standard Zicntr extension for base counters and timers, as 218 ratified in the 20191213 version of the unprivileged ISA 219 specification. 220 221 - const: zicond 222 description: 223 The standard Zicond extension for conditional arithmetic and 224 conditional-select/move operations as ratified in commit 95cf1f9 225 ("Add changes requested by Ved during signoff") of riscv-zicond. 226 227 - const: zicsr 228 description: | 229 The standard Zicsr extension for control and status register 230 instructions, as ratified in the 20191213 version of the 231 unprivileged ISA specification. 232 233 This does not include Chapter 10, "Counters", which documents 234 special case read-only CSRs, that were moved into the Zicntr and 235 Zihpm extensions after the ratification of the 20191213 version of 236 the unprivileged specification. 237 238 - const: zifencei 239 description: 240 The standard Zifencei extension for instruction-fetch fence, as 241 ratified in the 20191213 version of the unprivileged ISA 242 specification. 243 244 - const: zihintpause 245 description: 246 The standard Zihintpause extension for pause hints, as ratified in 247 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 248 249 - const: zihpm 250 description: 251 The standard Zihpm extension for hardware performance counters, as 252 ratified in the 20191213 version of the unprivileged ISA 253 specification. 254 255 - const: ztso 256 description: 257 The standard Ztso extension for total store ordering, as ratified 258 in commit 2e5236 ("Ztso is now ratified.") of the 259 riscv-isa-manual. 260 261additionalProperties: true 262... 263