1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27select: 28 properties: 29 compatible: 30 contains: 31 const: riscv 32 33properties: 34 riscv,isa: 35 description: 36 Identifies the specific RISC-V instruction set architecture 37 supported by the hart. These are documented in the RISC-V 38 User-Level ISA document, available from 39 https://riscv.org/specifications/ 40 41 Due to revisions of the ISA specification, some deviations 42 have arisen over time. 43 Notably, riscv,isa was defined prior to the creation of the 44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45 implies "zicntr_zicsr_zifencei_zihpm". 46 47 While the isa strings in ISA specification are case 48 insensitive, letters in the riscv,isa string must be all 49 lowercase. 50 $ref: /schemas/types.yaml#/definitions/string 51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 52 deprecated: true 53 54 riscv,isa-base: 55 description: 56 The base ISA implemented by this hart, as described by the 20191213 57 version of the unprivileged ISA specification. 58 enum: 59 - rv32i 60 - rv64i 61 62 riscv,isa-extensions: 63 $ref: /schemas/types.yaml#/definitions/string-array 64 minItems: 1 65 description: Extensions supported by the hart. 66 items: 67 anyOf: 68 # single letter extensions, in canonical order 69 - const: i 70 description: | 71 The base integer instruction set, as ratified in the 20191213 72 version of the unprivileged ISA specification. 73 74 This does not include Chapter 10, "Counters", which was moved into 75 the Zicntr and Zihpm extensions after the ratification of the 76 20191213 version of the unprivileged specification. 77 78 - const: m 79 description: 80 The standard M extension for integer multiplication and division, as 81 ratified in the 20191213 version of the unprivileged ISA 82 specification. 83 84 - const: a 85 description: 86 The standard A extension for atomic instructions, as ratified in the 87 20191213 version of the unprivileged ISA specification. 88 89 - const: f 90 description: 91 The standard F extension for single-precision floating point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: d 96 description: 97 The standard D extension for double-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: q 102 description: 103 The standard Q extension for quad-precision floating-point, as 104 ratified in the 20191213 version of the unprivileged ISA 105 specification. 106 107 - const: c 108 description: 109 The standard C extension for compressed instructions, as ratified in 110 the 20191213 version of the unprivileged ISA specification. 111 112 - const: v 113 description: 114 The standard V extension for vector operations, as ratified 115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116 encoding") of the riscv-v-spec. 117 118 - const: h 119 description: 120 The standard H extension for hypervisors as ratified in the 20191213 121 version of the privileged ISA specification. 122 123 # multi-letter extensions, sorted alphanumerically 124 - const: smaia 125 description: | 126 The standard Smaia supervisor-level extension for the advanced 127 interrupt architecture for machine-mode-visible csr and behavioural 128 changes to interrupts as frozen at commit ccbddab ("Merge pull 129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130 131 - const: smmpm 132 description: | 133 The standard Smmpm extension for M-mode pointer masking as 134 ratified at commit d70011dde6c2 ("Update to ratified state") 135 of riscv-j-extension. 136 137 - const: smnpm 138 description: | 139 The standard Smnpm extension for next-mode pointer masking as 140 ratified at commit d70011dde6c2 ("Update to ratified state") 141 of riscv-j-extension. 142 143 - const: smstateen 144 description: | 145 The standard Smstateen extension for controlling access to CSRs 146 added by other RISC-V extensions in H/S/VS/U/VU modes and as 147 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 148 149 - const: ssaia 150 description: | 151 The standard Ssaia supervisor-level extension for the advanced 152 interrupt architecture for supervisor-mode-visible csr and 153 behavioural changes to interrupts as frozen at commit ccbddab 154 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 155 156 - const: sscofpmf 157 description: | 158 The standard Sscofpmf supervisor-level extension for count overflow 159 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 160 to manually trigger workflow. (#2)") of riscv-count-overflow. 161 162 - const: ssnpm 163 description: | 164 The standard Ssnpm extension for next-mode pointer masking as 165 ratified at commit d70011dde6c2 ("Update to ratified state") 166 of riscv-j-extension. 167 168 - const: sstc 169 description: | 170 The standard Sstc supervisor-level extension for time compare as 171 ratified at commit 3f9ed34 ("Add ability to manually trigger 172 workflow. (#2)") of riscv-time-compare. 173 174 - const: svade 175 description: | 176 The standard Svade supervisor-level extension for SW-managed PTE A/D 177 bit updates as ratified in the 20240213 version of the privileged 178 ISA specification. 179 180 Both Svade and Svadu extensions control the hardware behavior when 181 the PTE A/D bits need to be set. The default behavior for the four 182 possible combinations of these extensions in the device tree are: 183 1) Neither Svade nor Svadu present in DT => It is technically 184 unknown whether the platform uses Svade or Svadu. Supervisor 185 software should be prepared to handle either hardware updating 186 of the PTE A/D bits or page faults when they need updated. 187 2) Only Svade present in DT => Supervisor must assume Svade to be 188 always enabled. 189 3) Only Svadu present in DT => Supervisor must assume Svadu to be 190 always enabled. 191 4) Both Svade and Svadu present in DT => Supervisor must assume 192 Svadu turned-off at boot time. To use Svadu, supervisor must 193 explicitly enable it using the SBI FWFT extension. 194 195 - const: svadu 196 description: | 197 The standard Svadu supervisor-level extension for hardware updating 198 of PTE A/D bits as ratified in the 20240528 version of the 199 privileged ISA specification. Please refer to Svade dt-binding 200 description for more details. 201 202 - const: svinval 203 description: 204 The standard Svinval supervisor-level extension for fine-grained 205 address-translation cache invalidation as ratified in the 20191213 206 version of the privileged ISA specification. 207 208 - const: svnapot 209 description: 210 The standard Svnapot supervisor-level extensions for napot 211 translation contiguity as ratified in the 20191213 version of the 212 privileged ISA specification. 213 214 - const: svpbmt 215 description: 216 The standard Svpbmt supervisor-level extensions for page-based 217 memory types as ratified in the 20191213 version of the privileged 218 ISA specification. 219 220 - const: svvptc 221 description: 222 The standard Svvptc supervisor-level extension for 223 address-translation cache behaviour with respect to invalid entries 224 as ratified at commit 4a69197e5617 ("Update to ratified state") of 225 riscv-svvptc. 226 227 - const: zaamo 228 description: | 229 The standard Zaamo extension for atomic memory operations as 230 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 231 (#1304)") of the unprivileged ISA specification. 232 233 - const: zabha 234 description: | 235 The Zabha extension for Byte and Halfword Atomic Memory Operations 236 as ratified at commit 49f49c842ff9 ("Update to Rafified state") of 237 riscv-zabha. 238 239 - const: zacas 240 description: | 241 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 242 is supported as ratified at commit 5059e0ca641c ("update to 243 ratified") of the riscv-zacas. 244 245 - const: zalrsc 246 description: | 247 The standard Zalrsc extension for load-reserved/store-conditional as 248 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 249 (#1304)") of the unprivileged ISA specification. 250 251 - const: zawrs 252 description: | 253 The Zawrs extension for entering a low-power state or for trapping 254 to a hypervisor while waiting on a store to a memory location, as 255 ratified in commit 98918c844281 ("Merge pull request #1217 from 256 riscv/zawrs") of riscv-isa-manual. 257 258 - const: zba 259 description: | 260 The standard Zba bit-manipulation extension for address generation 261 acceleration instructions as ratified at commit 6d33919 ("Merge pull 262 request #158 from hirooih/clmul-fix-loop-end-condition") of 263 riscv-bitmanip. 264 265 - const: zbb 266 description: | 267 The standard Zbb bit-manipulation extension for basic bit-manipulation 268 as ratified at commit 6d33919 ("Merge pull request #158 from 269 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 270 271 - const: zbc 272 description: | 273 The standard Zbc bit-manipulation extension for carry-less 274 multiplication as ratified at commit 6d33919 ("Merge pull request 275 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 276 277 - const: zbkb 278 description: 279 The standard Zbkb bitmanip instructions for cryptography as ratified 280 in version 1.0 of RISC-V Cryptography Extensions Volume I 281 specification. 282 283 - const: zbkc 284 description: 285 The standard Zbkc carry-less multiply instructions as ratified 286 in version 1.0 of RISC-V Cryptography Extensions Volume I 287 specification. 288 289 - const: zbkx 290 description: 291 The standard Zbkx crossbar permutation instructions as ratified 292 in version 1.0 of RISC-V Cryptography Extensions Volume I 293 specification. 294 295 - const: zbs 296 description: | 297 The standard Zbs bit-manipulation extension for single-bit 298 instructions as ratified at commit 6d33919 ("Merge pull request #158 299 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 300 301 - const: zca 302 description: | 303 The Zca extension part of Zc* standard extensions for code size 304 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 305 RV64 as it contains no instructions") of riscv-code-size-reduction, 306 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 307 of zc.adoc to src tree."). 308 309 - const: zcb 310 description: | 311 The Zcb extension part of Zc* standard extensions for code size 312 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 313 RV64 as it contains no instructions") of riscv-code-size-reduction, 314 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 315 of zc.adoc to src tree."). 316 317 - const: zcd 318 description: | 319 The Zcd extension part of Zc* standard extensions for code size 320 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 321 RV64 as it contains no instructions") of riscv-code-size-reduction, 322 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 323 of zc.adoc to src tree."). 324 325 - const: zcf 326 description: | 327 The Zcf extension part of Zc* standard extensions for code size 328 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 329 RV64 as it contains no instructions") of riscv-code-size-reduction, 330 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 331 of zc.adoc to src tree."). 332 333 - const: zcmop 334 description: 335 The standard Zcmop extension version 1.0, as ratified in commit 336 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 337 338 - const: zfa 339 description: 340 The standard Zfa extension for additional floating point 341 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 342 riscv-isa-manual. 343 344 - const: zfbfmin 345 description: 346 The standard Zfbfmin extension which provides minimal support for 347 16-bit half-precision brain floating-point instructions, as ratified 348 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 349 350 - const: zfh 351 description: 352 The standard Zfh extension for 16-bit half-precision binary 353 floating-point instructions, as ratified in commit 64074bc ("Update 354 version numbers for Zfh/Zfinx") of riscv-isa-manual. 355 356 - const: zfhmin 357 description: 358 The standard Zfhmin extension which provides minimal support for 359 16-bit half-precision binary floating-point instructions, as ratified 360 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 361 riscv-isa-manual. 362 363 - const: ziccrse 364 description: 365 The standard Ziccrse extension which provides forward progress 366 guarantee on LR/SC sequences, as ratified in commit b1d806605f87 367 ("Updated to ratified state.") of the riscv profiles specification. 368 369 - const: zk 370 description: 371 The standard Zk Standard Scalar cryptography extension as ratified 372 in version 1.0 of RISC-V Cryptography Extensions Volume I 373 specification. 374 375 - const: zkn 376 description: 377 The standard Zkn NIST algorithm suite extensions as ratified in 378 version 1.0 of RISC-V Cryptography Extensions Volume I 379 specification. 380 381 - const: zknd 382 description: | 383 The standard Zknd for NIST suite: AES decryption instructions as 384 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 385 specification. 386 387 - const: zkne 388 description: | 389 The standard Zkne for NIST suite: AES encryption instructions as 390 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 391 specification. 392 393 - const: zknh 394 description: | 395 The standard Zknh for NIST suite: hash function instructions as 396 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 397 specification. 398 399 - const: zkr 400 description: 401 The standard Zkr entropy source extension as ratified in version 402 1.0 of RISC-V Cryptography Extensions Volume I specification. 403 This string being present means that the CSR associated to this 404 extension is accessible at the privilege level to which that 405 device-tree has been provided. 406 407 - const: zks 408 description: 409 The standard Zks ShangMi algorithm suite extensions as ratified in 410 version 1.0 of RISC-V Cryptography Extensions Volume I 411 specification. 412 413 - const: zksed 414 description: | 415 The standard Zksed for ShangMi suite: SM4 block cipher instructions 416 as ratified in version 1.0 of RISC-V Cryptography Extensions 417 Volume I specification. 418 419 - const: zksh 420 description: | 421 The standard Zksh for ShangMi suite: SM3 hash function instructions 422 as ratified in version 1.0 of RISC-V Cryptography Extensions 423 Volume I specification. 424 425 - const: zkt 426 description: 427 The standard Zkt for data independent execution latency as ratified 428 in version 1.0 of RISC-V Cryptography Extensions Volume I 429 specification. 430 431 - const: zicbom 432 description: 433 The standard Zicbom extension for base cache management operations as 434 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 435 436 - const: zicbop 437 description: 438 The standard Zicbop extension for cache-block prefetch instructions 439 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 440 riscv-CMOs. 441 442 - const: zicboz 443 description: 444 The standard Zicboz extension for cache-block zeroing as ratified 445 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 446 447 - const: zicntr 448 description: 449 The standard Zicntr extension for base counters and timers, as 450 ratified in the 20191213 version of the unprivileged ISA 451 specification. 452 453 - const: zicond 454 description: 455 The standard Zicond extension for conditional arithmetic and 456 conditional-select/move operations as ratified in commit 95cf1f9 457 ("Add changes requested by Ved during signoff") of riscv-zicond. 458 459 - const: zicsr 460 description: | 461 The standard Zicsr extension for control and status register 462 instructions, as ratified in the 20191213 version of the 463 unprivileged ISA specification. 464 465 This does not include Chapter 10, "Counters", which documents 466 special case read-only CSRs, that were moved into the Zicntr and 467 Zihpm extensions after the ratification of the 20191213 version of 468 the unprivileged specification. 469 470 - const: zifencei 471 description: 472 The standard Zifencei extension for instruction-fetch fence, as 473 ratified in the 20191213 version of the unprivileged ISA 474 specification. 475 476 - const: zihintpause 477 description: 478 The standard Zihintpause extension for pause hints, as ratified in 479 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 480 481 - const: zihintntl 482 description: 483 The standard Zihintntl extension for non-temporal locality hints, as 484 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 485 riscv-isa-manual. 486 487 - const: zihpm 488 description: 489 The standard Zihpm extension for hardware performance counters, as 490 ratified in the 20191213 version of the unprivileged ISA 491 specification. 492 493 - const: zimop 494 description: 495 The standard Zimop extension version 1.0, as ratified in commit 496 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 497 498 - const: ztso 499 description: 500 The standard Ztso extension for total store ordering, as ratified 501 in commit 2e5236 ("Ztso is now ratified.") of the 502 riscv-isa-manual. 503 504 - const: zvbb 505 description: 506 The standard Zvbb extension for vectored basic bit-manipulation 507 instructions, as ratified in commit 56ed795 ("Update 508 riscv-crypto-spec-vector.adoc") of riscv-crypto. 509 510 - const: zvbc 511 description: 512 The standard Zvbc extension for vectored carryless multiplication 513 instructions, as ratified in commit 56ed795 ("Update 514 riscv-crypto-spec-vector.adoc") of riscv-crypto. 515 516 - const: zve32f 517 description: 518 The standard Zve32f extension for embedded processors, as ratified 519 in commit 6f702a2 ("Vector extensions are now ratified") of 520 riscv-v-spec. 521 522 - const: zve32x 523 description: 524 The standard Zve32x extension for embedded processors, as ratified 525 in commit 6f702a2 ("Vector extensions are now ratified") of 526 riscv-v-spec. 527 528 - const: zve64d 529 description: 530 The standard Zve64d extension for embedded processors, as ratified 531 in commit 6f702a2 ("Vector extensions are now ratified") of 532 riscv-v-spec. 533 534 - const: zve64f 535 description: 536 The standard Zve64f extension for embedded processors, as ratified 537 in commit 6f702a2 ("Vector extensions are now ratified") of 538 riscv-v-spec. 539 540 - const: zve64x 541 description: 542 The standard Zve64x extension for embedded processors, as ratified 543 in commit 6f702a2 ("Vector extensions are now ratified") of 544 riscv-v-spec. 545 546 - const: zvfbfmin 547 description: 548 The standard Zvfbfmin extension for minimal support for vectored 549 16-bit half-precision brain floating-point instructions, as ratified 550 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 551 552 - const: zvfbfwma 553 description: 554 The standard Zvfbfwma extension for vectored half-precision brain 555 floating-point widening multiply-accumulate instructions, as ratified 556 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 557 558 - const: zvfh 559 description: 560 The standard Zvfh extension for vectored half-precision 561 floating-point instructions, as ratified in commit e2ccd05 562 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 563 564 - const: zvfhmin 565 description: 566 The standard Zvfhmin extension for vectored minimal half-precision 567 floating-point instructions, as ratified in commit e2ccd05 568 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 569 570 - const: zvkb 571 description: 572 The standard Zvkb extension for vector cryptography bit-manipulation 573 instructions, as ratified in commit 56ed795 ("Update 574 riscv-crypto-spec-vector.adoc") of riscv-crypto. 575 576 - const: zvkg 577 description: 578 The standard Zvkg extension for vector GCM/GMAC instructions, as 579 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 580 of riscv-crypto. 581 582 - const: zvkn 583 description: 584 The standard Zvkn extension for NIST algorithm suite instructions, as 585 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 586 of riscv-crypto. 587 588 - const: zvknc 589 description: 590 The standard Zvknc extension for NIST algorithm suite with carryless 591 multiply instructions, as ratified in commit 56ed795 ("Update 592 riscv-crypto-spec-vector.adoc") of riscv-crypto. 593 594 - const: zvkned 595 description: 596 The standard Zvkned extension for Vector AES block cipher 597 instructions, as ratified in commit 56ed795 ("Update 598 riscv-crypto-spec-vector.adoc") of riscv-crypto. 599 600 - const: zvkng 601 description: 602 The standard Zvkng extension for NIST algorithm suite with GCM 603 instructions, as ratified in commit 56ed795 ("Update 604 riscv-crypto-spec-vector.adoc") of riscv-crypto. 605 606 - const: zvknha 607 description: | 608 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 609 hash (SHA-256 only) instructions, as ratified in commit 610 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 611 612 - const: zvknhb 613 description: | 614 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 615 hash (SHA-256 and SHA-512) instructions, as ratified in commit 616 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 617 618 - const: zvks 619 description: 620 The standard Zvks extension for ShangMi algorithm suite 621 instructions, as ratified in commit 56ed795 ("Update 622 riscv-crypto-spec-vector.adoc") of riscv-crypto. 623 624 - const: zvksc 625 description: 626 The standard Zvksc extension for ShangMi algorithm suite with 627 carryless multiplication instructions, as ratified in commit 56ed795 628 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 629 630 - const: zvksed 631 description: | 632 The standard Zvksed extension for ShangMi suite: SM4 block cipher 633 instructions, as ratified in commit 56ed795 ("Update 634 riscv-crypto-spec-vector.adoc") of riscv-crypto. 635 636 - const: zvksh 637 description: | 638 The standard Zvksh extension for ShangMi suite: SM3 secure hash 639 instructions, as ratified in commit 56ed795 ("Update 640 riscv-crypto-spec-vector.adoc") of riscv-crypto. 641 642 - const: zvksg 643 description: 644 The standard Zvksg extension for ShangMi algorithm suite with GCM 645 instructions, as ratified in commit 56ed795 ("Update 646 riscv-crypto-spec-vector.adoc") of riscv-crypto. 647 648 - const: zvkt 649 description: 650 The standard Zvkt extension for vector data-independent execution 651 latency, as ratified in commit 56ed795 ("Update 652 riscv-crypto-spec-vector.adoc") of riscv-crypto. 653 654 # vendor extensions, each extension sorted alphanumerically under the 655 # vendor they belong to. Vendors are sorted alphanumerically as well. 656 657 # Andes 658 - const: xandespmu 659 description: 660 The Andes Technology performance monitor extension for counter overflow 661 and privilege mode filtering. For more details, see Counter Related 662 Registers in the AX45MP datasheet. 663 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 664 665 # MIPS 666 - const: xmipsexectl 667 description: 668 The MIPS extension for execution control as documented in 669 https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf 670 671 # SiFive 672 - const: xsfcease 673 description: 674 SiFive CEASE Instruction Extensions Specification. 675 See more details in 676 https://www.sifive.com/document-file/freedom-u740-c000-manual 677 678 - const: xsfcflushdlone 679 description: 680 SiFive L1D Cache Flush Instruction Extensions Specification. 681 See more details in 682 https://www.sifive.com/document-file/freedom-u740-c000-manual 683 684 - const: xsfpgflushdlone 685 description: 686 SiFive PGFLUSH Instruction Extensions for the power management. The 687 CPU will flush the L1D and enter the cease state after executing 688 the instruction. 689 690 - const: xsfvqmaccdod 691 description: 692 SiFive Int8 Matrix Multiplication Extensions Specification. 693 See more details in 694 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 695 696 - const: xsfvqmaccqoq 697 description: 698 SiFive Int8 Matrix Multiplication Extensions Specification. 699 See more details in 700 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 701 702 - const: xsfvfnrclipxfqf 703 description: 704 SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. 705 See more details in 706 https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions 707 708 - const: xsfvfwmaccqqq 709 description: 710 SiFive Matrix Multiply Accumulate Instruction Extensions Specification. 711 See more details in 712 https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction 713 714 # T-HEAD 715 - const: xtheadvector 716 description: 717 The T-HEAD specific 0.7.1 vector implementation as written in 718 https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. 719 720 allOf: 721 - if: 722 contains: 723 const: d 724 then: 725 contains: 726 const: f 727 # Zcb depends on Zca 728 - if: 729 contains: 730 const: zcb 731 then: 732 contains: 733 const: zca 734 # Zcd depends on Zca and D 735 - if: 736 contains: 737 const: zcd 738 then: 739 allOf: 740 - contains: 741 const: zca 742 - contains: 743 const: d 744 # Zcf depends on Zca and F 745 - if: 746 contains: 747 const: zcf 748 then: 749 allOf: 750 - contains: 751 const: zca 752 - contains: 753 const: f 754 # Zcmop depends on Zca 755 - if: 756 contains: 757 const: zcmop 758 then: 759 contains: 760 const: zca 761 # Zfbfmin depends on F 762 - if: 763 contains: 764 const: zfbfmin 765 then: 766 contains: 767 const: f 768 # Zvfbfmin depends on V or Zve32f 769 - if: 770 contains: 771 const: zvfbfmin 772 then: 773 oneOf: 774 - contains: 775 const: v 776 - contains: 777 const: zve32f 778 # Zvfbfwma depends on Zfbfmin and Zvfbfmin 779 - if: 780 contains: 781 const: zvfbfwma 782 then: 783 allOf: 784 - contains: 785 const: zfbfmin 786 - contains: 787 const: zvfbfmin 788 # Zacas depends on Zaamo 789 - if: 790 contains: 791 const: zacas 792 then: 793 contains: 794 const: zaamo 795 796 - if: 797 contains: 798 const: zve32x 799 then: 800 contains: 801 const: zicsr 802 803 - if: 804 contains: 805 const: zve32f 806 then: 807 allOf: 808 - contains: 809 const: f 810 - contains: 811 const: zve32x 812 813 - if: 814 contains: 815 const: zve64x 816 then: 817 contains: 818 const: zve32x 819 820 - if: 821 contains: 822 const: zve64f 823 then: 824 allOf: 825 - contains: 826 const: f 827 - contains: 828 const: zve32f 829 - contains: 830 const: zve64x 831 832 - if: 833 contains: 834 const: zve64d 835 then: 836 allOf: 837 - contains: 838 const: d 839 - contains: 840 const: zve64f 841 842 - if: 843 contains: 844 anyOf: 845 - const: zvbc 846 - const: zvkn 847 - const: zvknc 848 - const: zvkng 849 - const: zvknhb 850 - const: zvksc 851 then: 852 contains: 853 anyOf: 854 - const: v 855 - const: zve64x 856 857 - if: 858 contains: 859 anyOf: 860 - const: zvbb 861 - const: zvkb 862 - const: zvkg 863 - const: zvkned 864 - const: zvknha 865 - const: zvksed 866 - const: zvksh 867 - const: zvks 868 - const: zvkt 869 then: 870 contains: 871 anyOf: 872 - const: v 873 - const: zve32x 874 875allOf: 876 # Zcf extension does not exist on rv64 877 - if: 878 properties: 879 riscv,isa-extensions: 880 contains: 881 const: zcf 882 riscv,isa-base: 883 contains: 884 const: rv64i 885 then: 886 properties: 887 riscv,isa-extensions: 888 not: 889 contains: 890 const: zcf 891 892additionalProperties: true 893... 894