1# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: RISC-V ISA extensions 8 9maintainers: 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 13 14description: | 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 17 are "vendor" extensions. 18 This document defines properties that indicate whether a hart supports a 19 given extension. 20 21 Once a standard extension has been ratified, no changes in behaviour can be 22 made without the creation of a new extension. 23 The properties for standard extensions therefore map to their originally 24 ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25 See the "i" property for more information. 26 27properties: 28 riscv,isa: 29 description: 30 Identifies the specific RISC-V instruction set architecture 31 supported by the hart. These are documented in the RISC-V 32 User-Level ISA document, available from 33 https://riscv.org/specifications/ 34 35 Due to revisions of the ISA specification, some deviations 36 have arisen over time. 37 Notably, riscv,isa was defined prior to the creation of the 38 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 39 implies "zicntr_zicsr_zifencei_zihpm". 40 41 While the isa strings in ISA specification are case 42 insensitive, letters in the riscv,isa string must be all 43 lowercase. 44 $ref: /schemas/types.yaml#/definitions/string 45 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ 46 deprecated: true 47 48 riscv,isa-base: 49 description: 50 The base ISA implemented by this hart, as described by the 20191213 51 version of the unprivileged ISA specification. 52 enum: 53 - rv32i 54 - rv64i 55 56 riscv,isa-extensions: 57 $ref: /schemas/types.yaml#/definitions/string-array 58 minItems: 1 59 description: Extensions supported by the hart. 60 items: 61 anyOf: 62 # single letter extensions, in canonical order 63 - const: i 64 description: | 65 The base integer instruction set, as ratified in the 20191213 66 version of the unprivileged ISA specification. 67 68 This does not include Chapter 10, "Counters", which was moved into 69 the Zicntr and Zihpm extensions after the ratification of the 70 20191213 version of the unprivileged specification. 71 72 - const: m 73 description: 74 The standard M extension for integer multiplication and division, as 75 ratified in the 20191213 version of the unprivileged ISA 76 specification. 77 78 - const: a 79 description: 80 The standard A extension for atomic instructions, as ratified in the 81 20191213 version of the unprivileged ISA specification. 82 83 - const: f 84 description: 85 The standard F extension for single-precision floating point, as 86 ratified in the 20191213 version of the unprivileged ISA 87 specification. 88 89 - const: d 90 description: 91 The standard D extension for double-precision floating-point, as 92 ratified in the 20191213 version of the unprivileged ISA 93 specification. 94 95 - const: q 96 description: 97 The standard Q extension for quad-precision floating-point, as 98 ratified in the 20191213 version of the unprivileged ISA 99 specification. 100 101 - const: c 102 description: 103 The standard C extension for compressed instructions, as ratified in 104 the 20191213 version of the unprivileged ISA specification. 105 106 - const: b 107 description: 108 The standard B extension for bit manipulation instructions, as 109 ratified in the 20240411 version of the unprivileged ISA 110 specification. The B standard extension comprises instructions 111 provided by the Zba, Zbb, and Zbs extensions. 112 113 - const: v 114 description: 115 The standard V extension for vector operations, as ratified 116 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 117 encoding") of the riscv-v-spec. 118 119 - const: h 120 description: 121 The standard H extension for hypervisors as ratified in the RISC-V 122 Instruction Set Manual, Volume II Privileged Architecture, 123 Document Version 20211203. 124 125 # multi-letter extensions, sorted alphanumerically 126 - const: sha 127 description: | 128 The standard Sha extension for augmented hypervisor extension as 129 ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 130 ("rva23/rvb23 ratified"). 131 132 Sha captures the full set of features that are mandated to be 133 supported along with the H extension. Sha comprises the following 134 extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, 135 Shvstvecd, and Ssstateen. 136 137 - const: shcounterenw 138 description: | 139 The standard Shcounterenw extension for support writable enables 140 in hcounteren for any supported counter, as ratified in RISC-V 141 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 142 ratified state.") 143 144 - const: shgatpa 145 description: | 146 The standard Shgatpa extension indicates that for each supported 147 virtual memory scheme SvNN supported in satp, the corresponding 148 hgatp SvNNx4 mode must be supported. The hgatp mode Bare must 149 also be supported. It is ratified in RISC-V Profiles Version 1.0, 150 with commit b1d806605f87 ("Updated to ratified state.") 151 152 - const: shtvala 153 description: | 154 The standard Shtvala extension for htval be written with the 155 faulting guest physical address in all circumstances permitted by 156 the ISA. It is ratified in RISC-V Profiles Version 1.0, with 157 commit b1d806605f87 ("Updated to ratified state.") 158 159 - const: shvsatpa 160 description: | 161 The standard Shvsatpa extension for vsatp supporting all translation 162 modes supported in satp, as ratified in RISC-V Profiles Version 1.0, 163 with commit b1d806605f87 ("Updated to ratified state.") 164 165 - const: shvstvala 166 description: | 167 The standard Shvstvala extension for vstval provides all needed 168 values as ratified in RISC-V Profiles Version 1.0, with commit 169 b1d806605f87 ("Updated to ratified state.") 170 171 - const: shvstvecd 172 description: | 173 The standard Shvstvecd extension for vstvec supporting Direct mode, 174 as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 175 ("Updated to ratified state.") 176 177 - const: smaia 178 description: | 179 The standard Smaia supervisor-level extension for the advanced 180 interrupt architecture for machine-mode-visible csr and behavioural 181 changes to interrupts as frozen at commit ccbddab ("Merge pull 182 request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 183 184 - const: smmpm 185 description: | 186 The standard Smmpm extension for M-mode pointer masking as 187 ratified at commit d70011dde6c2 ("Update to ratified state") 188 of riscv-j-extension. 189 190 - const: smnpm 191 description: | 192 The standard Smnpm extension for next-mode pointer masking as 193 ratified at commit d70011dde6c2 ("Update to ratified state") 194 of riscv-j-extension. 195 196 - const: smstateen 197 description: | 198 The standard Smstateen extension for controlling access to CSRs 199 added by other RISC-V extensions in H/S/VS/U/VU modes and as 200 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. 201 202 - const: ssaia 203 description: | 204 The standard Ssaia supervisor-level extension for the advanced 205 interrupt architecture for supervisor-mode-visible csr and 206 behavioural changes to interrupts as frozen at commit ccbddab 207 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 208 209 - const: ssccptr 210 description: | 211 The standard Ssccptr extension for main memory (cacheability and 212 coherence) hardware page-table reads, as ratified in RISC-V 213 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 214 ratified state.") 215 216 - const: sscofpmf 217 description: | 218 The standard Sscofpmf supervisor-level extension for count overflow 219 and mode-based filtering as ratified at commit 01d1df0 ("Add ability 220 to manually trigger workflow. (#2)") of riscv-count-overflow. 221 222 - const: sscounterenw 223 description: | 224 The standard Sscounterenw extension for support writable enables 225 in scounteren for any supported counter, as ratified in RISC-V 226 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 227 ratified state.") 228 229 - const: ssnpm 230 description: | 231 The standard Ssnpm extension for next-mode pointer masking as 232 ratified at commit d70011dde6c2 ("Update to ratified state") 233 of riscv-j-extension. 234 235 - const: ssstateen 236 description: | 237 The standard Ssstateen extension for supervisor-mode view of the 238 state-enable extension, as ratified in RISC-V Profiles Version 1.0, 239 with commit b1d806605f87 ("Updated to ratified state.") 240 241 - const: sstc 242 description: | 243 The standard Sstc supervisor-level extension for time compare as 244 ratified at commit 3f9ed34 ("Add ability to manually trigger 245 workflow. (#2)") of riscv-time-compare. 246 247 - const: sstvala 248 description: | 249 The standard Sstvala extension for stval provides all needed values 250 as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 251 ("Updated to ratified state.") 252 253 - const: sstvecd 254 description: | 255 The standard Sstvecd extension for stvec supports Direct mode as 256 ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 257 ("Updated to ratified state.") 258 259 - const: ssu64xl 260 description: | 261 The standard Ssu64xl extension for UXLEN=64 must be supported, as 262 ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 263 ("Updated to ratified state.") 264 265 - const: supm 266 description: | 267 The standard Supm extension for pointer masking support in user 268 mode (U-mode) as ratified at commit d70011dde6c2 ("Update to 269 ratified state") of riscv-j-extension. 270 271 Supm represents a combination of underlying hardware capability 272 (Smnpm or Ssnpm), U-mode consumer privilege level, and M/S-mode 273 software configuration that enables pointer masking for U-mode. 274 275 DO NOT include this property in device trees targeting privileged 276 system software (S-mode or M-mode). 277 278 This property is only appropriate in device trees provided to 279 U-mode software where the next-higher-privilege-mode supports 280 Smnpm or Ssnpm and enables it for U-mode. 281 282 - const: svade 283 description: | 284 The standard Svade supervisor-level extension for SW-managed PTE A/D 285 bit updates as ratified in the 20240213 version of the privileged 286 ISA specification. 287 288 Both Svade and Svadu extensions control the hardware behavior when 289 the PTE A/D bits need to be set. The default behavior for the four 290 possible combinations of these extensions in the device tree are: 291 1) Neither Svade nor Svadu present in DT => It is technically 292 unknown whether the platform uses Svade or Svadu. Supervisor 293 software should be prepared to handle either hardware updating 294 of the PTE A/D bits or page faults when they need updated. 295 2) Only Svade present in DT => Supervisor must assume Svade to be 296 always enabled. 297 3) Only Svadu present in DT => Supervisor must assume Svadu to be 298 always enabled. 299 4) Both Svade and Svadu present in DT => Supervisor must assume 300 Svadu turned-off at boot time. To use Svadu, supervisor must 301 explicitly enable it using the SBI FWFT extension. 302 303 - const: svadu 304 description: | 305 The standard Svadu supervisor-level extension for hardware updating 306 of PTE A/D bits as ratified in the 20240528 version of the 307 privileged ISA specification. Please refer to Svade dt-binding 308 description for more details. 309 310 - const: svinval 311 description: 312 The standard Svinval supervisor-level extension for fine-grained 313 address-translation cache invalidation as ratified in the RISC-V 314 Instruction Set Manual, Volume II Privileged Architecture, 315 Document Version 20211203. 316 317 - const: svnapot 318 description: 319 The standard Svnapot supervisor-level extensions for napot 320 translation contiguity as ratified in the RISC-V Instruction Set 321 Manual, Volume II Privileged Architecture, Document Version 322 20211203. 323 324 - const: svpbmt 325 description: 326 The standard Svpbmt supervisor-level extensions for page-based 327 memory types as ratified in the RISC-V Instruction Set Manual, 328 Volume II Privileged Architecture, Document Version 20211203. 329 330 - const: svrsw60t59b 331 description: 332 The Svrsw60t59b extension for providing two more bits[60:59] to 333 PTE/PMD entry as ratified at commit 28bde925e7a7 ("PTE Reserved 334 for SW bits 60:59") of riscv-non-isa/riscv-iommu. 335 336 - const: svvptc 337 description: 338 The standard Svvptc supervisor-level extension for 339 address-translation cache behaviour with respect to invalid entries 340 as ratified at commit 4a69197e5617 ("Update to ratified state") of 341 riscv-svvptc. 342 343 - const: za64rs 344 description: 345 The standard Za64rs extension for reservation set size of at most 346 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit 347 b1d806605f87 ("Updated to ratified state.") 348 349 - const: zaamo 350 description: | 351 The standard Zaamo extension for atomic memory operations as 352 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 353 (#1304)") of the unprivileged ISA specification. 354 355 - const: zabha 356 description: | 357 The Zabha extension for Byte and Halfword Atomic Memory Operations 358 as ratified at commit 49f49c842ff9 ("Update to Rafified state") of 359 riscv-zabha. 360 361 - const: zacas 362 description: | 363 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions 364 is supported as ratified at commit 5059e0ca641c ("update to 365 ratified") of the riscv-zacas. 366 367 - const: zalasr 368 description: | 369 The standard Zalasr extension for load-acquire/store-release as frozen 370 at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. 371 372 - const: zalrsc 373 description: | 374 The standard Zalrsc extension for load-reserved/store-conditional as 375 ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text 376 (#1304)") of the unprivileged ISA specification. 377 378 - const: zawrs 379 description: | 380 The Zawrs extension for entering a low-power state or for trapping 381 to a hypervisor while waiting on a store to a memory location, as 382 ratified in commit 98918c844281 ("Merge pull request #1217 from 383 riscv/zawrs") of riscv-isa-manual. 384 385 - const: zba 386 description: | 387 The standard Zba bit-manipulation extension for address generation 388 acceleration instructions as ratified at commit 6d33919 ("Merge pull 389 request #158 from hirooih/clmul-fix-loop-end-condition") of 390 riscv-bitmanip. 391 392 - const: zbb 393 description: | 394 The standard Zbb bit-manipulation extension for basic bit-manipulation 395 as ratified at commit 6d33919 ("Merge pull request #158 from 396 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 397 398 - const: zbc 399 description: | 400 The standard Zbc bit-manipulation extension for carry-less 401 multiplication as ratified at commit 6d33919 ("Merge pull request 402 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 403 404 - const: zbkb 405 description: 406 The standard Zbkb bitmanip instructions for cryptography as ratified 407 in version 1.0 of RISC-V Cryptography Extensions Volume I 408 specification. 409 410 - const: zbkc 411 description: 412 The standard Zbkc carry-less multiply instructions as ratified 413 in version 1.0 of RISC-V Cryptography Extensions Volume I 414 specification. 415 416 - const: zbkx 417 description: 418 The standard Zbkx crossbar permutation instructions as ratified 419 in version 1.0 of RISC-V Cryptography Extensions Volume I 420 specification. 421 422 - const: zbs 423 description: | 424 The standard Zbs bit-manipulation extension for single-bit 425 instructions as ratified at commit 6d33919 ("Merge pull request #158 426 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 427 428 - const: zca 429 description: | 430 The Zca extension part of Zc* standard extensions for code size 431 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 432 RV64 as it contains no instructions") of riscv-code-size-reduction, 433 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 434 of zc.adoc to src tree."). 435 436 - const: zcb 437 description: | 438 The Zcb extension part of Zc* standard extensions for code size 439 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 440 RV64 as it contains no instructions") of riscv-code-size-reduction, 441 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 442 of zc.adoc to src tree."). 443 444 - const: zcd 445 description: | 446 The Zcd extension part of Zc* standard extensions for code size 447 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 448 RV64 as it contains no instructions") of riscv-code-size-reduction, 449 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 450 of zc.adoc to src tree."). 451 452 - const: zcf 453 description: | 454 The Zcf extension part of Zc* standard extensions for code size 455 reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on 456 RV64 as it contains no instructions") of riscv-code-size-reduction, 457 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed 458 of zc.adoc to src tree."). 459 460 - const: zcmop 461 description: 462 The standard Zcmop extension version 1.0, as ratified in commit 463 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. 464 465 - const: zfa 466 description: 467 The standard Zfa extension for additional floating point 468 instructions, as ratified in commit 056b6ff ("Zfa is ratified") of 469 riscv-isa-manual. 470 471 - const: zfbfmin 472 description: 473 The standard Zfbfmin extension which provides minimal support for 474 16-bit half-precision brain floating-point instructions, as ratified 475 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 476 477 - const: zfh 478 description: 479 The standard Zfh extension for 16-bit half-precision binary 480 floating-point instructions, as ratified in commit 64074bc ("Update 481 version numbers for Zfh/Zfinx") of riscv-isa-manual. 482 483 - const: zfhmin 484 description: 485 The standard Zfhmin extension which provides minimal support for 486 16-bit half-precision binary floating-point instructions, as ratified 487 in commit 64074bc ("Update version numbers for Zfh/Zfinx") of 488 riscv-isa-manual. 489 490 - const: ziccamoa 491 description: 492 The standard Ziccamoa extension for main memory (cacheability and 493 coherence) must support all atomics in A, as ratified in RISC-V 494 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 495 ratified state.") 496 497 - const: ziccif 498 description: 499 The standard Ziccif extension for main memory (cacheability and 500 coherence) instruction fetch atomicity, as ratified in RISC-V 501 Profiles Version 1.0, with commit b1d806605f87 ("Updated to 502 ratified state.") 503 504 - const: zicclsm 505 description: 506 The standard Zicclsm extension for main memory (cacheability and 507 coherence) must support misaligned loads and stores, as ratified 508 in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated 509 to ratified state.") 510 511 - const: ziccrse 512 description: 513 The standard Ziccrse extension which provides forward progress 514 guarantee on LR/SC sequences, as ratified in commit b1d806605f87 515 ("Updated to ratified state.") of the riscv profiles specification. 516 517 - const: zilsd 518 description: 519 The standard Zilsd extension which provides support for aligned 520 register-pair load and store operations in 32-bit instruction 521 encodings, as ratified in commit f88abf1 ("Integrating 522 load/store pair for RV32 with the main manual") of riscv-isa-manual. 523 524 - const: zclsd 525 description: 526 The Zclsd extension implements the compressed (16-bit) version of the 527 Load/Store Pair for RV32. As with Zilsd, this extension was ratified 528 in commit f88abf1 ("Integrating load/store pair for RV32 with the 529 main manual") of riscv-isa-manual. 530 531 - const: zk 532 description: 533 The standard Zk Standard Scalar cryptography extension as ratified 534 in version 1.0 of RISC-V Cryptography Extensions Volume I 535 specification. 536 537 - const: zkn 538 description: 539 The standard Zkn NIST algorithm suite extensions as ratified in 540 version 1.0 of RISC-V Cryptography Extensions Volume I 541 specification. 542 543 - const: zknd 544 description: | 545 The standard Zknd for NIST suite: AES decryption instructions as 546 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 547 specification. 548 549 - const: zkne 550 description: | 551 The standard Zkne for NIST suite: AES encryption instructions as 552 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 553 specification. 554 555 - const: zknh 556 description: | 557 The standard Zknh for NIST suite: hash function instructions as 558 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I 559 specification. 560 561 - const: zkr 562 description: 563 The standard Zkr entropy source extension as ratified in version 564 1.0 of RISC-V Cryptography Extensions Volume I specification. 565 This string being present means that the CSR associated to this 566 extension is accessible at the privilege level to which that 567 device-tree has been provided. 568 569 - const: zks 570 description: 571 The standard Zks ShangMi algorithm suite extensions as ratified in 572 version 1.0 of RISC-V Cryptography Extensions Volume I 573 specification. 574 575 - const: zksed 576 description: | 577 The standard Zksed for ShangMi suite: SM4 block cipher instructions 578 as ratified in version 1.0 of RISC-V Cryptography Extensions 579 Volume I specification. 580 581 - const: zksh 582 description: | 583 The standard Zksh for ShangMi suite: SM3 hash function instructions 584 as ratified in version 1.0 of RISC-V Cryptography Extensions 585 Volume I specification. 586 587 - const: zkt 588 description: 589 The standard Zkt for data independent execution latency as ratified 590 in version 1.0 of RISC-V Cryptography Extensions Volume I 591 specification. 592 593 - const: zicbom 594 description: 595 The standard Zicbom extension for base cache management operations as 596 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 597 598 - const: zicbop 599 description: 600 The standard Zicbop extension for cache-block prefetch instructions 601 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 602 riscv-CMOs. 603 604 - const: zicboz 605 description: 606 The standard Zicboz extension for cache-block zeroing as ratified 607 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 608 609 - const: zicfilp 610 description: | 611 The standard Zicfilp extension for enforcing forward edge 612 control-flow integrity as ratified in commit 3f8e450 ("merge 613 pull request #227 from ved-rivos/0709") of riscv-cfi 614 github repo. 615 616 - const: zicfiss 617 description: | 618 The standard Zicfiss extension for enforcing backward edge 619 control-flow integrity as ratified in commit 3f8e450 ("merge 620 pull request #227 from ved-rivos/0709") of riscv-cfi 621 github repo. 622 623 - const: zicntr 624 description: 625 The standard Zicntr extension for base counters and timers, as 626 ratified in the 20191213 version of the unprivileged ISA 627 specification. 628 629 - const: zicond 630 description: 631 The standard Zicond extension for conditional arithmetic and 632 conditional-select/move operations as ratified in commit 95cf1f9 633 ("Add changes requested by Ved during signoff") of riscv-zicond. 634 635 - const: zicsr 636 description: | 637 The standard Zicsr extension for control and status register 638 instructions, as ratified in the 20191213 version of the 639 unprivileged ISA specification. 640 641 This does not include Chapter 10, "Counters", which documents 642 special case read-only CSRs, that were moved into the Zicntr and 643 Zihpm extensions after the ratification of the 20191213 version of 644 the unprivileged specification. 645 646 - const: zifencei 647 description: 648 The standard Zifencei extension for instruction-fetch fence, as 649 ratified in the 20191213 version of the unprivileged ISA 650 specification. 651 652 - const: zihintpause 653 description: 654 The standard Zihintpause extension for pause hints, as ratified in 655 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 656 657 - const: zihintntl 658 description: 659 The standard Zihintntl extension for non-temporal locality hints, as 660 ratified in commit 0dc91f5 ("Zihintntl is ratified") of the 661 riscv-isa-manual. 662 663 - const: zihpm 664 description: 665 The standard Zihpm extension for hardware performance counters, as 666 ratified in the 20191213 version of the unprivileged ISA 667 specification. 668 669 - const: zimop 670 description: 671 The standard Zimop extension version 1.0, as ratified in commit 672 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. 673 674 - const: ztso 675 description: 676 The standard Ztso extension for total store ordering, as ratified 677 in commit 2e5236 ("Ztso is now ratified.") of the 678 riscv-isa-manual. 679 680 - const: zvbb 681 description: 682 The standard Zvbb extension for vectored basic bit-manipulation 683 instructions, as ratified in commit 56ed795 ("Update 684 riscv-crypto-spec-vector.adoc") of riscv-crypto. 685 686 - const: zvbc 687 description: 688 The standard Zvbc extension for vectored carryless multiplication 689 instructions, as ratified in commit 56ed795 ("Update 690 riscv-crypto-spec-vector.adoc") of riscv-crypto. 691 692 - const: zve32f 693 description: 694 The standard Zve32f extension for embedded processors, as ratified 695 in commit 6f702a2 ("Vector extensions are now ratified") of 696 riscv-v-spec. 697 698 - const: zve32x 699 description: 700 The standard Zve32x extension for embedded processors, as ratified 701 in commit 6f702a2 ("Vector extensions are now ratified") of 702 riscv-v-spec. 703 704 - const: zve64d 705 description: 706 The standard Zve64d extension for embedded processors, as ratified 707 in commit 6f702a2 ("Vector extensions are now ratified") of 708 riscv-v-spec. 709 710 - const: zve64f 711 description: 712 The standard Zve64f extension for embedded processors, as ratified 713 in commit 6f702a2 ("Vector extensions are now ratified") of 714 riscv-v-spec. 715 716 - const: zve64x 717 description: 718 The standard Zve64x extension for embedded processors, as ratified 719 in commit 6f702a2 ("Vector extensions are now ratified") of 720 riscv-v-spec. 721 722 - const: zvfbfmin 723 description: 724 The standard Zvfbfmin extension for minimal support for vectored 725 16-bit half-precision brain floating-point instructions, as ratified 726 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 727 728 - const: zvfbfwma 729 description: 730 The standard Zvfbfwma extension for vectored half-precision brain 731 floating-point widening multiply-accumulate instructions, as ratified 732 in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. 733 734 - const: zvfh 735 description: 736 The standard Zvfh extension for vectored half-precision 737 floating-point instructions, as ratified in commit e2ccd05 738 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 739 740 - const: zvfhmin 741 description: 742 The standard Zvfhmin extension for vectored minimal half-precision 743 floating-point instructions, as ratified in commit e2ccd05 744 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec. 745 746 - const: zvkb 747 description: 748 The standard Zvkb extension for vector cryptography bit-manipulation 749 instructions, as ratified in commit 56ed795 ("Update 750 riscv-crypto-spec-vector.adoc") of riscv-crypto. 751 752 - const: zvkg 753 description: 754 The standard Zvkg extension for vector GCM/GMAC instructions, as 755 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 756 of riscv-crypto. 757 758 - const: zvkn 759 description: 760 The standard Zvkn extension for NIST algorithm suite instructions, as 761 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") 762 of riscv-crypto. 763 764 - const: zvknc 765 description: 766 The standard Zvknc extension for NIST algorithm suite with carryless 767 multiply instructions, as ratified in commit 56ed795 ("Update 768 riscv-crypto-spec-vector.adoc") of riscv-crypto. 769 770 - const: zvkned 771 description: 772 The standard Zvkned extension for Vector AES block cipher 773 instructions, as ratified in commit 56ed795 ("Update 774 riscv-crypto-spec-vector.adoc") of riscv-crypto. 775 776 - const: zvkng 777 description: 778 The standard Zvkng extension for NIST algorithm suite with GCM 779 instructions, as ratified in commit 56ed795 ("Update 780 riscv-crypto-spec-vector.adoc") of riscv-crypto. 781 782 - const: zvknha 783 description: | 784 The standard Zvknha extension for NIST suite: vector SHA-2 secure, 785 hash (SHA-256 only) instructions, as ratified in commit 786 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 787 788 - const: zvknhb 789 description: | 790 The standard Zvknhb extension for NIST suite: vector SHA-2 secure, 791 hash (SHA-256 and SHA-512) instructions, as ratified in commit 792 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 793 794 - const: zvks 795 description: 796 The standard Zvks extension for ShangMi algorithm suite 797 instructions, as ratified in commit 56ed795 ("Update 798 riscv-crypto-spec-vector.adoc") of riscv-crypto. 799 800 - const: zvksc 801 description: 802 The standard Zvksc extension for ShangMi algorithm suite with 803 carryless multiplication instructions, as ratified in commit 56ed795 804 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. 805 806 - const: zvksed 807 description: | 808 The standard Zvksed extension for ShangMi suite: SM4 block cipher 809 instructions, as ratified in commit 56ed795 ("Update 810 riscv-crypto-spec-vector.adoc") of riscv-crypto. 811 812 - const: zvksh 813 description: | 814 The standard Zvksh extension for ShangMi suite: SM3 secure hash 815 instructions, as ratified in commit 56ed795 ("Update 816 riscv-crypto-spec-vector.adoc") of riscv-crypto. 817 818 - const: zvksg 819 description: 820 The standard Zvksg extension for ShangMi algorithm suite with GCM 821 instructions, as ratified in commit 56ed795 ("Update 822 riscv-crypto-spec-vector.adoc") of riscv-crypto. 823 824 - const: zvkt 825 description: 826 The standard Zvkt extension for vector data-independent execution 827 latency, as ratified in commit 56ed795 ("Update 828 riscv-crypto-spec-vector.adoc") of riscv-crypto. 829 830 # vendor extensions, each extension sorted alphanumerically under the 831 # vendor they belong to. Vendors are sorted alphanumerically as well. 832 833 # Andes 834 - const: xandespmu 835 description: 836 The Andes Technology performance monitor extension for counter overflow 837 and privilege mode filtering. For more details, see Counter Related 838 Registers in the AX45MP datasheet. 839 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf 840 841 # MIPS 842 - const: xmipsexectl 843 description: 844 The MIPS extension for execution control as documented in 845 https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf 846 847 # SiFive 848 - const: xsfcease 849 description: 850 SiFive CEASE Instruction Extensions Specification. 851 See more details in 852 https://www.sifive.com/document-file/freedom-u740-c000-manual 853 854 - const: xsfcflushdlone 855 description: 856 SiFive L1D Cache Flush Instruction Extensions Specification. 857 See more details in 858 https://www.sifive.com/document-file/freedom-u740-c000-manual 859 860 - const: xsfpgflushdlone 861 description: 862 SiFive PGFLUSH Instruction Extensions for the power management. The 863 CPU will flush the L1D and enter the cease state after executing 864 the instruction. 865 866 - const: xsfvqmaccdod 867 description: 868 SiFive Int8 Matrix Multiplication Extensions Specification. 869 See more details in 870 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 871 872 - const: xsfvqmaccqoq 873 description: 874 SiFive Int8 Matrix Multiplication Extensions Specification. 875 See more details in 876 https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification 877 878 - const: xsfvfnrclipxfqf 879 description: 880 SiFive FP32-to-int8 Ranged Clip Instructions Extensions Specification. 881 See more details in 882 https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions 883 884 - const: xsfvfwmaccqqq 885 description: 886 SiFive Matrix Multiply Accumulate Instruction Extensions Specification. 887 See more details in 888 https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction 889 890 # T-HEAD 891 - const: xtheadvector 892 description: 893 The T-HEAD specific 0.7.1 vector implementation as written in 894 https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. 895 896 allOf: 897 - if: 898 contains: 899 const: d 900 then: 901 contains: 902 const: f 903 # B comprises Zba, Zbb, and Zbs 904 - if: 905 contains: 906 const: b 907 then: 908 allOf: 909 - contains: 910 const: zba 911 - contains: 912 const: zbb 913 - contains: 914 const: zbs 915 # Zba, Zbb, Zbs together require B 916 - if: 917 allOf: 918 - contains: 919 const: zba 920 - contains: 921 const: zbb 922 - contains: 923 const: zbs 924 then: 925 contains: 926 const: b 927 # Supm depends on Smnpm or Ssnpm 928 - if: 929 contains: 930 const: supm 931 then: 932 oneOf: 933 - contains: 934 const: smnpm 935 - contains: 936 const: ssnpm 937 # Za64rs and Ziccrse depend on Zalrsc or A 938 - if: 939 contains: 940 anyOf: 941 - const: za64rs 942 - const: ziccrse 943 then: 944 oneOf: 945 - contains: 946 const: zalrsc 947 - contains: 948 const: a 949 # Zcb depends on Zca 950 - if: 951 contains: 952 const: zcb 953 then: 954 contains: 955 const: zca 956 # Zcd depends on Zca and D 957 - if: 958 contains: 959 const: zcd 960 then: 961 allOf: 962 - contains: 963 const: zca 964 - contains: 965 const: d 966 # Zcf depends on Zca and F 967 - if: 968 contains: 969 const: zcf 970 then: 971 allOf: 972 - contains: 973 const: zca 974 - contains: 975 const: f 976 # Zcmop depends on Zca 977 - if: 978 contains: 979 const: zcmop 980 then: 981 contains: 982 const: zca 983 # Zfbfmin depends on F 984 - if: 985 contains: 986 const: zfbfmin 987 then: 988 contains: 989 const: f 990 # Ziccamoa depends on Zaamo or A 991 - if: 992 contains: 993 const: ziccamoa 994 then: 995 oneOf: 996 - contains: 997 const: zaamo 998 - contains: 999 const: a 1000 # Zvfbfmin depends on V or Zve32f 1001 - if: 1002 contains: 1003 const: zvfbfmin 1004 then: 1005 oneOf: 1006 - contains: 1007 const: v 1008 - contains: 1009 const: zve32f 1010 # Zvfbfwma depends on Zfbfmin and Zvfbfmin 1011 - if: 1012 contains: 1013 const: zvfbfwma 1014 then: 1015 allOf: 1016 - contains: 1017 const: zfbfmin 1018 - contains: 1019 const: zvfbfmin 1020 # Zacas depends on Zaamo 1021 - if: 1022 contains: 1023 const: zacas 1024 then: 1025 contains: 1026 const: zaamo 1027 1028 - if: 1029 contains: 1030 const: zve32x 1031 then: 1032 contains: 1033 const: zicsr 1034 1035 - if: 1036 contains: 1037 const: zve32f 1038 then: 1039 allOf: 1040 - contains: 1041 const: f 1042 - contains: 1043 const: zve32x 1044 1045 - if: 1046 contains: 1047 const: zve64x 1048 then: 1049 contains: 1050 const: zve32x 1051 1052 - if: 1053 contains: 1054 const: zve64f 1055 then: 1056 allOf: 1057 - contains: 1058 const: f 1059 - contains: 1060 const: zve32f 1061 - contains: 1062 const: zve64x 1063 1064 - if: 1065 contains: 1066 const: zve64d 1067 then: 1068 allOf: 1069 - contains: 1070 const: d 1071 - contains: 1072 const: zve64f 1073 1074 - if: 1075 contains: 1076 anyOf: 1077 - const: zvbc 1078 - const: zvkn 1079 - const: zvknc 1080 - const: zvkng 1081 - const: zvknhb 1082 - const: zvksc 1083 then: 1084 contains: 1085 anyOf: 1086 - const: v 1087 - const: zve64x 1088 1089 - if: 1090 contains: 1091 anyOf: 1092 - const: zvbb 1093 - const: zvkb 1094 - const: zvkg 1095 - const: zvkned 1096 - const: zvknha 1097 - const: zvksed 1098 - const: zvksh 1099 - const: zvks 1100 - const: zvkt 1101 then: 1102 contains: 1103 anyOf: 1104 - const: v 1105 - const: zve32x 1106 # Zclsd depends on Zilsd and Zca 1107 - if: 1108 contains: 1109 anyOf: 1110 - const: zclsd 1111 then: 1112 contains: 1113 allOf: 1114 - const: zilsd 1115 - const: zca 1116 1117allOf: 1118 # Zcf extension does not exist on rv64 1119 - if: 1120 properties: 1121 riscv,isa-extensions: 1122 contains: 1123 const: zcf 1124 riscv,isa-base: 1125 contains: 1126 const: rv64i 1127 then: 1128 properties: 1129 riscv,isa-extensions: 1130 not: 1131 contains: 1132 const: zcf 1133 # Zilsd extension does not exist on rv64 1134 - if: 1135 properties: 1136 riscv,isa-base: 1137 contains: 1138 const: rv64i 1139 then: 1140 properties: 1141 riscv,isa-extensions: 1142 not: 1143 contains: 1144 const: zilsd 1145 1146additionalProperties: true 1147... 1148